TOF bit... 7 8 87 7 76 6 65 5 54 43 32 21 0 1 ...previous valueCNTchannel (n) outputcounteroverflowchannel (n) match indown counting channel (n) match inup countingchannel (n) match indown countingcounteroverflowCHF bitMOD = 0x0008CnV = 0x0005Figure 41-28. CPWM signal with ELSB:ELSA = 1:0If (ELSB:ELSA = X:1), then the channel (n) output is forced low at the channel (n)match (FTM counter = CnV) when counting down, and it is forced high at the channel (n)match when counting up. See the following figure.TOF bit... 7 8 87 7 76 6 65 5 54 43 32 21 0 1 ...previous valueCNTchannel (n) outputcounteroverflowchannel (n) match indown counting channel (n) match inup counting channel (n) match indown countingcounteroverflowCHF bitMOD = 0x0008CnV = 0x0005Figure 41-29. CPWM signal with ELSB:ELSA = X:1If (CnV = 0x0000) or CnV is a negative value, that is (CnV[15] = 1), then the channel (n)output is a 0% duty cycle CPWM signal and CHF bit is not set even when there is thechannel (n) match.If CnV is a positive value, that is (CnV[15] = 0), (CnV ≥ MOD), and (MOD ≠ 0x0000),then the channel (n) output is a 100% duty cycle CPWM signal and CHF bit is not seteven when there is the channel (n) match. This implies that the usable range of periodsset by MOD is 0x0001 through 0x7FFE, 0x7FFF if you do not need to generate a 100%duty cycle CPWM signal. This is not a significant limitation because the resulting periodis much longer than required for normal applications.The CPWM mode must not be used when the FTM counter is a free running counter.41.5.9 Combine modeThe Combine mode is selected when:• QUADEN = 0Functional DescriptionMWCT101xS Series Reference Manual, Rev. 3, 07/20191208 NXP Semiconductors
