Table 2-4. Core modules (continued)Module DescriptionNVIC The Armv7-M exception model and nested-vectored interrupt controller (NVIC)implement a relocatable vector table supporting many external interrupts, a singlenon-maskable interrupt (NMI), and priority levels.The NVIC replaces shadow registers with equivalent system and simplifiedprogrammability. The NVIC contains the address of the function to execute for aparticular handler. The address is fetched via the instruction port allowing parallelregister stacking and look-up. The first sixteen entries are allocated to Arm internalsources, with the others mapping to MCU-defined interrupts.AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) isto detect asynchronous wake-up events in stop modes and then signal to clockcontrol logic to resume system clocking. After clock restart, the NVIC observes thepending interrupt and performs the normal interrupt or event processing.Debug interfaces Most of the debug capability on this device is based on the Arm CoreSight™architecture. Following debug interfaces are supported:• Serial wire IEEE 1149.1 JTAG debug Port (SWJ-DP), with 2 pin serial wiredebug (SWD) for external debugger• Debug Watchpoint and Trace (DWT), with four configurable comparators ashardware watchpoints• Serial wire output (SWO)-synchronous trace data support• Instrumentation Trace Macrocell (ITM) with software and hardware trace,plus time stamping• Flash Patch and Breakpoints (FPB) with ability to patch code and data fromcode space to system space• Serial Wire Viewer (SWV): A trace capability providing displays of reads,writes, exceptions, PC Samples and printf.• Supports 4 pin trace interface2.7.2 System modulesThe following system modules are available on this device.Table 2-5. System modulesModule DescriptionMiscellaneous control module (MCM) The MCM includes miscellaneous control logic for Core and System modules.System integration module (SIM) The SIM includes miscellaneous device configuration and status registers.PORT The Port Control and Interrupt (PORT) module provides support for port control,digital filtering, and external interrupt functions.GPIO The general-purpose input and output (GPIO) module communicates to theprocessor core via a zero wait state interface for maximum pin performance. TheGPIO registers support 8-bit, 16-bit or 32-bit accesses.Crossbar switch (AXBS-Lite) The AXBS-Lite connects bus masters and bus slaves, allowing all bus masters toaccess different bus slaves simultaneously and providing arbitration among the busmasters when they access the same slave.System Memory protection unit (MPU) The system MPU provides memory protection and task isolation. It concurrentlymonitors all bus master transactions for the slave connections.Table continues on the next page...Module functional categoriesMWCT101xS Series Reference Manual, Rev. 3, 07/201960 NXP Semiconductors
