• Modifications to clock gating control bits are prohibited.• Flash programming/erasing is not allowed.To enter HSRUN mode (with 112 MHz SPLL as clock source):1. Disable SPLL. Configure FIRC as the RUN mode and HSRUN mode clock sourceby writing 0011 to SCG_RCCR[SCS] and SCG_HCCR[SCS].2. Configure PMPROT[AHSRUN] to allow HSRUN.3. Write 11 to SMC_PMCTRL[RUNM] to enter HSRUN. (Now system will enterHSRUN mode with FIRC configured as system clock source).4. Reconfigure PLL for 112MHz and enable it.5. Switch to PLL as the clock source by configuring SCG_HCCR[SCS] as 0110.Entry to HSRUN mode (with 80 MHz SPLL as clock source):1. Configure SPLL at 80MHz as the RUN mode and HSRUN mode clock source bywriting 0110 to SCG_RCCR[SCS] and SCG_HCCR[SCS].2. Configure PMPROT[AHSRUN] to allow HSRUN.3. Write 11 to SMC_PMCTRL[RUNM] to enter HSRUN.Before increasing clock frequencies, the PMSTAT register should be polled to determinewhen the system has completed entry into HSRUN mode. To reenter normal RUN mode,clear PMCTRL[RUNM]. Any reset also clears PMCTRL[RUNM] and causes the systemto exit to normal RUN mode after the MCU exits its reset flow.35.4.4 Stop modesThe various stop modes are selected by setting the appropriate fields in PMPROT andPMCTRL. The selected stop mode is entered during the sleep-now or sleep-on-exit entrywith the SLEEPDEEP bit set in the System Control Register in the Arm core.The available stop modes are:• Normal Stop (STOP)• Very-Low Power Stop (VLPS)35.4.4.1 STOP modeSTOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set inthe System Control Register in the Arm core.The SCG module can be configured to leave the reference clocks running.Chapter 35 System Mode Controller (SMC)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 957
