50.8 AHB-APAHB-AP provides the debugger access to all memory and registers in the system,including processor registers through the NVIC. System access is independent of theprocessor status. AHB-AP does not perform back-to-back transactions on the bus, so alltransactions are non-sequential. AHB-AP can perform unaligned and bit-bandtransactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-APtransactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supportedsideband signal called HABORT. This signal is driven into the Bus Matrix, which resetsthe Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditchdebugging such as read/stop/reset the core. AHB-AP transactions are little-endian.The MPU includes default settings and protections for the Region Descriptor 0 (RGD0)such that the Debugger always has access to the entire address space and those rightscannot be changed by the core or any other bus master.For a short period at the start of a system reset event, the system security status is beingdetermined and debugger access to all AHB-AP transactions is blocked. The MDM-APStatus register is accessible and can be monitored to determine when this initial period iscompleted. After this initial period, if system reset is held via assertion of the RESET_bpin, the debugger has access via the bus matrix to the private peripheral bus to configurethe debug IP even while system reset is asserted. While in system reset, access to othermemory and register resources, accessed over the crossbar switch, is blocked.50.9 ITMThe Instrumentation Trace Macrocell (ITM) is an application-driven trace source thatsupports printf style debugging to trace operating system and application events, andemits diagnostic system information. The ITM emits trace information as packets. Thereare four sources that can generate packets. If multiple sources generate packets at thesame time, the ITM arbitrates the order in which packets are output. The four sources indecreasing order of priority are:1. Software trace: Software can write directly to ITM stimulus registers. This emitspackets.2. Hardware trace: The DWT generates these packets, and the ITM emits them.3. Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. The counter is clocked either by the Cortex-M4 clock or by the bit clock rate of the Serial Wire Viewer (SWV) output.AHB-APMWCT101xS Series Reference Manual, Rev. 3, 07/20191722 NXP Semiconductors
