1. For TCM sizes, see MCM chapter. Device specific reset values of LMDR0 and LMDR1 registers are documented in Chip-specific MCM information.NOTEThe DFLASH value indicated above for WCT1016S is for nonEEE mode, i.e., complete FlexNVM (512 KB) being used asDFLASH. For EEE mode, this size will be 448 KB.30.2 OverviewThe Miscellaneous System Control Module (MSCM) contains CPU configurationregisters and on-chip memory controller registers.The MSCM block diagram is shown below in Figure 30-1 :CPU ConfigurationRegistersOn-Chip MemoryRegistersMSCMReset Configuration(RCON)On-Chip MemoryBus Interface to CPU or other Bus MastersFigure 30-1. MSCM Block Diagram30.3 Chip Configuration and BootThe device’s logical definition is controlled via chip-specific configuration bits,supported memory sizes and packing options. Collectively, these configuration bitsdefine a reset configuration value (RCON).Once the core has fetched the needed reset vector(s), it is expected that core and systemconfiguration information is read from a globally-accessible slave peripheral thatproperly converts the information into more appropriate values. More specifically, theOverviewMWCT101xS Series Reference Manual, Rev. 3, 07/2019658 NXP Semiconductors
