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Figure 29-3 illustrates the SRAM accesses within the device.SRAM controllerBackdoorSRAM_LSRAM_UFrontdoorFigure 29-3. SRAM access diagramThe following simultaneous accesses can be made to different logical halves of theSRAM:• Core code and core system• Core code and non-core master• Core system and non-core masterNOTETwo non-core masters cannot access SRAM simultaneously.The required arbitration and serialization is provided by thecrossbar switch. The SRAM_L and SRAM_U arbitration iscontrolled by the SRAM controller based on the configurationbits in the MCM module.NOTEBurst-access cannot occur across the 0x2000_0000 boundarythat separates the two SRAM arrays. The two arrays should betreated as separate memory ranges for burst accesses.29.4.3 Cache FunctionThe cache on this device is structured as follows. The cache has a 2-way set-associativecache structure with a total size of 4 KBytes for the Code Cache. The cache has 32-bitaddress and data paths and a 16-byte line size. The cache tags and data storage use single-port, synchronous RAMs.Chapter 29 Local Memory Controller (LMEM)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 651