51.2.3.3 Bypass modeWhen no test operation is required, the BYPASS instruction can be loaded to place theJTAGC block into bypass mode. When in bypass mode, the single-bit bypass shiftregister is used to provide a minimum-length serial path to shift data between TDI andTDO.51.3 External signal descriptionThe JTAGC consists of a set of signals that connect to off-chip development tools andallow access to test support functions. The JTAGC signals are outlined in the followingtable and described in the following sections.Table 51-2. JTAG signal propertiesName I/O Function Reset stateTCK Input Test clock Weak pulldownTDI Input Test data in Weak pullupTDO Output Test data out High Z1TMS Input Test mode select Weak pullup1. TDO output buffer enable is negated when the JTAGC is not in the Shift-IR or Shift-DR states. A weak pull may beimplemented at the TDO pad for use when JTAGC is inactive.51.3.1 Test clock input (TCK)Test Clock Input (TCK) is an input pin used to synchronize the test logic and controlregister access through the TAP.51.3.2 Test data input (TDI)Test Data Input (TDI) is an input pin that receives serial test instructions and data. TDI issampled on the rising edge of TCK.51.3.3 Test data output (TDO)Test Data Output (TDO) is an output pin that transmits serial output for test instructionsand data. TDO is tristateable and is actively driven only in the Shift-IR and Shift-DRstates of the TAP controller state machine, which is described in TAP controller statemachine.External signal descriptionMWCT101xS Series Reference Manual, Rev. 3, 07/20191730 NXP Semiconductors
