7.1.3 Debug facilitiesThis chip has extensive debug capabilities including run control and tracing capabilities.This is a standard Arm debug port that supports JTAG and SWD interfaces.7.1.4 CachesThis device includes one 4 KB code cache to minimize the performance impact ofmemory access latencies. The code cache exists on the I/D bus, and there is no cache onthe system bus.Features of the cache are:• 2-way set associative• 4 word lines• Lines can be individually flushed• Entire cache can be flushed at once7.1.4.1 ControlFor control purposes, the cache can be in one of these states:1. Write Back / Write Allocate (WBWA)2. Write Through3. No cacheFor each defined region there will be 2 bits allocated on the control register (seePCCRMR that determines the cache state for the memory region associated with thissection. The user can only "lower" the cache attribute, given the fixed relationship ofWBWA > WT > NC - so, you can demote a WBWA region to either WT or NC, you candemote a WT space to NC. In order to change the state upwards a system reset isrequired.NOTESee LMEM for the cache reset states.7.1.5 Core privilege levelsThe Arm documentation uses different terms than this document to distinguish betweenprivilege levels.Chapter 7 Core OverviewMWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 99
