Field Function1b - Allows the given access type to occur5M0PEBus Master 0 Process Identifier Enable0b - Do not include the process identifier in the evaluation1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation4-3M0SMBus Master 0 Supervisor Mode Access ControlDefines the access controls for bus master 0 in Supervisor mode.00b - r/w/x; read, write and execute allowed01b - r/x; read and execute allowed, but no write10b - r/w; read and write allowed, but no execute11b - Same as User mode defined in M0UM2-0M0UMBus Master 0 User Mode Access ControlDefines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls readpermissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For eachbit:0b - An attempted access of that mode may be terminated with an access error (if not allowed byanother descriptor) and the access not performed1b - Allows the given access type to occur13.4.13 Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)13.4.13.1 OffsetFor n = 1 to 15:Register OffsetRGDAACn 800h + (n × 4h)13.4.13.2 FunctionBecause software may adjust only the access controls within a region descriptor(RGDn_WORD2) as different tasks execute, an alternate programming view of this 32-bit entity is available. Writing to this register does not affect the descriptor’s valid bit.MPU register descriptionsMWCT101xS Series Reference Manual, Rev. 3, 07/2019228 NXP Semiconductors
