Program flashFlash memory configuration fieldFlexNVM base addressProgram flash memory base addressFlash memory base addressRegistersFlexNVMFlexRAMFlexRAM base addressmemoryFigure 3-1. Flash memory map3.4 Peripheral bridge (AIPS-Lite) memory mapThe peripheral memory map is accessible via a crossbar slave port.There are three regions associated with peripheral space, as shown in the following table.Table 3-1. Regions associated with peripheral spaceAddress space Region description0x4000_0000–0x4001_FFFF A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for on-platform peripheral devices. AIPS-Lite generates unique module enables for all 32spaces.0x4002_0000–0x4007_FFFF A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for off-platform modules. AIPS-Lite generates unique module enables for all 96 spaces.0x400F_F000 A 4 KB region for accessing the GPIO module. This block is connected to theAMBA bus via the port splitter and provides direct master access without incurringwait states associated with accesses via the AIPS-Lite modules. The GPIO isimplemented only in the upper space of this region (4 KB beginning at0x400F_F000).Modules that are disabled via their clock gate control bits in the PCC/SIM registersdisable the associated AIPS-Lite slots. Access to any address within an unimplemented ordisabled peripheral bridge slot results in a transfer error termination.NOTEWhile trying to access memory map region of unavailablefeature (See SIM_SDID[FEATURES]) with correspondingPeripheral bridge (AIPS-Lite) memory mapMWCT101xS Series Reference Manual, Rev. 3, 07/201966 NXP Semiconductors
