TRGMUXTrigger input 1Trigger input 2Trigger input 6Trigger input 3[SELx]...001...010...011...100...101...110...111Trigger input 4Trigger input 5Trigger input 7To peripheraltrigger inputsTrigger disabled ...000Up to four outputs per peripheralTrigger input N** Up to 255 trigger inputs may be available for SEL0, SEL1, and SEL2. For SEL3, up to 127trigger inputs may be available. When the number of trigger inputs is 255, SEL3 is notavailable and becomes reserved. See the chip-specific TRGMUX information for themaximum number of trigger inputs supported on this device.[SEL0] selects the trigger for output 0[SEL1] selects the trigger for output 1[SEL2] selects the trigger for output 2[SEL3] selects the trigger for output 3output xFigure 17-4. TRGMUX block diagramEach peripheral has its own dedicated TRGMUX register. See each peripheral'sTRGMUX register for details.17.4 Memory map and register definitionThe TRGMUX registers contain fields for selecting trigger sources for peripheralmodules.TRGMUX registers can be written only in supervisor mode.17.4.1 TRGMUX register descriptions17.4.1.1 TRGMUX Memory mapTable 17-2. Select Bit FieldsField DescriptionSELx This read/write field is used to configure the MUX select for the peripheral trigger inputs.Memory map and register definitionMWCT101xS Series Reference Manual, Rev. 3, 07/2019378 NXP Semiconductors
