21.4.3.2.1 Unlocking the WatchdogThe unlock sequence is a write to the CNT register of 0xC520 followed by 0xD928within 16 bus clocks at any time after the watchdog has been configured. On completingthe unlock sequence, the user must reconfigure the watchdog within 128 bus clocks;otherwise, the watchdog closes the unlock window.NOTEDue to the 128 bus clocks requirement for reconfiguring thewatchdog, some delays must be inserted before executingSTOP or WAIT instructions after reconfiguring the watchdog.This ensures that the watchdog's new configuration takes effectbefore the MCU enters low power mode. Otherwise, the MCUmay not be waken up from low power mode.The example codes can be found at end of this chapter.21.4.4 Using interrupts to delay resets• When interrupts are enabled (CS[INT] = 1): After a reset-triggering event (like acounter timeout or invalid refresh attempt), the watchdog first generates an interruptrequest. Next, the watchdog delays 128 bus clocks (from the interrupt vector fetch,not the reset-triggering event) before forcing a reset, to allow the interrupt serviceroutine (ISR) to perform tasks (like analyzing the stack to debug code).• When interrupts are disabled (CS[INT] = 0): the watchdog does not delay theforcing a reset.21.4.5 Backup resetNOTEA clock source other than the bus clock must be used as thereference clock for the counter; otherwise, the backup resetfunction is not available.The backup reset function is a safeguard feature that independently generates a reset incase the main WDOG logic loses its clock (the bus clock) and can no longer monitor thecounter. If the watchdog counter overflows twice in succession (without an interveningreset), the backup reset function takes effect and generates a reset.Chapter 21 Watchdog timer (WDOG)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 467
