Chapter 50Debug50.1 IntroductionThe debug capability on this device is based on the Arm CoreSight™ architecture and isconfigured on each device to provide the maximum flexibility as allowed by therestrictions of the pinout and other available resources.Table 50-1. Supported debug interfacesChip Supported debug interfacesIEEE 1149.1 JTAG Serial WireDebug(SWD)SWO 4-pin parallel traceport1WCT1014S Yes Yes Yes NoWCT1015S Yes Yes Yes NoWCT1016S Yes Yes Yes Yes1. Overrides the value of Supported Port Size Register of TPIU (at location 0x000)The basic Cortex-M4 debug architecture is very flexible. The following diagram showsthe topology of the core debug architecture and its components.MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1713
