Table 48-4. UART Transmit Configuration (continued)Register Value CommentsSHIFTBUFn Data to transmit Transmit data can be written toSHIFTBUF[7:0] to initiate an 8-bittransfer, use the Shifter Status Flag toindicate when data can be written usinginterrupt or DMA request. Can supportMSB first transfer by writing toSHIFTBUFBBS[7:0] register instead.48.5.2 UART ReceiveUART receive can be supported using one Timer, one Shifter and one Pin (two Timersand two Pins if supporting RTS). The start and stop bit verification is handledautomatically and multiple transfers can be supported using the DMA controller. Thetimer status flag can be used to indicate when the stop bit of each word is received.Triple voting of the received data is not supported by FlexIO, data is sampled only oncein the middle of each bit. Another timer can be used to implement a glitch filter on theincoming data, another Timer can also be used to detect an idle line of programmablelength. Break characters will cause the error flag to set and the shifter buffer register willreturn 0x00.FlexIO does not support automatic verification of parity bits.Table 48-5. UART Receiver ConfigurationRegister Value CommentsSHIFTCFGn 0x0000_0032 Configure start bit of 0 and stop bit of 1.SHIFTCTLn 0x0080_0001 Configure receive using Timer 0 onnegedge of clock with input data on Pin0. Can invert input data by settingPINPOL.TIMCMPn 0x0000_0F01 Configure 8-bit transfer with baud rate ofdivide by 4 of the FlexIO clock. SetTIMCMP[15:8] = (number of bits x 2) - 1.Set TIMCMP[7:0] = (baud rate divider /2) - 1.TIMCFGn 0x0204_2422 Configure start bit, stop bit, enable onpin posedge and disable on compare.Enable resynchronization to receiveddata with TIMOUT=0x2 andTIMRST=0x4.TIMCTLn 0x0000_0081 Configure dual 8-bit counter usinginverted Pin 0 input.Table continues on the next page...Application InformationMWCT101xS Series Reference Manual, Rev. 3, 07/20191552 NXP Semiconductors
