start value, or decrement on selected trigger inputs or previous channel timeout(when channels are chained). By chaining timer channels, applications can achievelarger timeout durations.• In capture mode: the timer can be used to perform measurements as the timer valueis captured (in the timer value register) when a selected trigger input is asserted. Thetimer can support once-off or multiple measurements (like frequency measurements).The timer channels operate on an asynchronous clock, which is independent from theregister read/write access clock. Clock synchronization between the clock domainsensures normal operations.42.2.2 Block DiagramThe next figure shows a detailed block diagram for an LPIT module. The programmingmodel comprises of a global register set (common to all timer channels), and registers foreach timer channel (that control their respective timer channels). Access to these registersgets synchronized to the asynchronous peripheral clock, then affects the timer channelregisters.• Each timer channel contains a 32-bit counter that loads the starting value and downcounts on every peripheral clock's positive edge.• After reaching a zero value (a channel timer timeout), a trigger output is generated.• The counter enable is controlled using a timer enable register control bit, external orinternal triggers or via previous channel timeout (when using timer chaining).• After a channel timer timeout, an interrupt bit is also set, to tell the CPU about thetimer timeout.For more details, see the functional description section.Chapter 42 Low Power Interrupt Timer (LPIT)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1299
