bit (the bypass register) when conducting an EXTEST type of instruction through theboundary scan register. CLAMP also asserts the internal system reset for the MCU toforce a predictable internal state.51.5.4.8 BYPASS instructionBYPASS selects the bypass register, creating a single-bit shift register path between TDIand TDO. BYPASS enhances test efficiency by reducing the overall shift path when notest operation of the MCU is required. This allows more rapid movement of test data toand from other components on a board that are required to perform test functions. Whenthe BYPASS instruction is active the system logic operates normally.51.5.5 Boundary scanThe boundary scan technique allows signals at component boundaries to be controlledand observed through the shift-register stage associated with each pad. Each stage is partof a larger boundary scan register cell, and cells for each pad are interconnected seriallyto form a shift-register chain around the border of the design. The boundary scan registerconsists of this shift-register chain, and is connected between TDI and TDO when theEXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded. The shift-registerchain contains a serial input and serial output, as well as clock and control signals.51.6 Initialization/application informationThe test logic is a static logic design, and TCK can be stopped in either a high or lowstate without loss of data. However, the system clock is not synchronized to TCKinternally. Any mixed operation using both the test logic and the system functional logicrequires external synchronization.To initialize the JTAGC block and enable access to registers, the following sequence isrequired:1. Place the JTAGC in reset through TAP controller state machine transitions controlledby TMS.2. Load the appropriate instruction for the test or action to be performed.Chapter 51 JTAG Controller (JTAGC)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1739
