Table 14-1. Register reset values (continued)Register WCT1014S WCT1015S WCT1016SOPACRA 4400_4444 4400_4444 4400_4444OPACRB 0000_4400 0000_4400 0004_4440OPACRC 0440_0044 0440_0044 0440_0044OPACRD 4444_0400 4444_0400 4444_0400OPACRE 4000_0040 4000_0040 4000_0040OPACRF 4444_4400 4444_4400 4444_4400OPACRG 0040_0000 0040_0000 0040_4400OPACRH 0040_0000 0040_0000 0040_0000OPACRI 0404_4440 0404_4440 0404_4444OPACRJ 0044_0000 0044_4044 0044_4044OPACRK 0004_0000 0004_0000 4404_0040OPACRL 0000_0444 0000_0444 0400_044414.2 IntroductionThe peripheral bridge converts the crossbar switch interface to an interface that canaccess most of the slave peripherals on this chip.The peripheral bridge occupies 64 MB of the address space, which is divided intoperipheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.See the memory map chapter for details on slot assignments.) The bridge includesseparate clock enable inputs for each of the slots to accommodate slower peripherals.14.2.1 FeaturesKey features of the peripheral bridge are:• Supports peripheral slots with 8-, 16-, and 32-bit datapath width• Programming model provides memory protection functionality14.2.2 General operationThe slave devices connected to the peripheral bridge are modules which contain aprogramming model of control and status registers. The system masters read and writethese registers through the peripheral bridge.IntroductionMWCT101xS Series Reference Manual, Rev. 3, 07/2019238 NXP Semiconductors
