18.2.3 Block DiagramThis figure shows the EWM block diagram.Clock DividerLogicLPO_CLKLow PowerClock Clock GatingCellANDEnableEWM_CTRL[EWMEN]EWM_CLKPRESCALER[CLK_DIV]8-bit CounterORCounter ValueReset toCounterEWM RefreshAnd/EWM_out OutputControlMechanismEWM_CMPH[COMPAREH]EWM_CMPL[COMPAREL]EWM RefreshedEWM_outCounteroverflowEWM_inEWM Service RegisterCPUResetFigure 18-1. EWM Block Diagram18.3 EWM Signal DescriptionsThe EWM has two external signals, as shown in the following table.NOTEAll active-low signals are now represented with the suffix "_b"throughout the chapter.Table 18-2. EWM Signal DescriptionsSignal Description I/OEWM_in EWM input for safety status of external safety circuits. The polarity ofEWM_in is programmable using the EWM_CTRL[ASSIN] bit. The defaultpolarity is active low.IEWM_OUT_b EWM reset out signal OEWM Signal DescriptionsMWCT101xS Series Reference Manual, Rev. 3, 07/2019420 NXP Semiconductors
