Table 39-5. Comparator sample/filter maximum latencies (continued)Mode # C0[EN]C0[WE]C0[SE]C0[FILTER_CNT] Co[FPR] Operation Maximum latency13B 1 0 0 0x01 > 0x00 TPD + (C0[FPR] * Tper) + Tper4A 1 0 1 > 0x01 X Sampled, Filtered mode TPD + (C0[FILTER_CNT] *TSAMPLE) + Tper4B 1 0 0 > 0x01 > 0x00 TPD + (C0[FILTER_CNT] *C0[FPR] x Tper) + Tper5A 1 1 0 0x00 X Windowed mode TPD + Tper5B 1 1 0 X 0x00 TPD + Tper6 1 1 0 0x01 0x01 - 0xFF Windowed / ResampledmodeTPD + (C0[FPR] * Tper) +2Tper7 1 1 0 > 0x01 0x01 - 0xFF Windowed / Filtered mode TPD + (C0[FILTER_CNT] *C0[FPR] x Tper) + 2Tper1. TPD represents the intrinsic delay of the analog component plus the polarity select logic. TSAMPLE is the clock period of theexternal sample clock. Tper is the period of the bus clock.39.10 InterruptsThe CMP module is capable of generating an interrupt on either the rising- or falling-edge of the comparator output, or both. Assuming the CMP DMA enable bit is not set,the following table gives the conditions in which the interrupt request is asserted anddeasserted.Table 39-6. CMP interrupt generationsWhen ThenC0[IER] and C0[CFR] are set The interrupt request is assertedC0[IEF] and C0[CFF] are set The interrupt request is assertedC0[IER] and C0[CFR] are cleared for a rising-edge interrupt The interrupt request is deassertedC0[IEF] and C0[CFF] are cleared for a falling-edge interrupt The interrupt request is deasserted39.11 DMA supportNormally, the CMP generates a CPU interrupt if there is a change on the COUT. WhenDMA support is enabled by setting C0[DMAEN] and the interrupt is enabled by settingC0[IER], C0[IEF], or both, the corresponding change on COUT forces a DMA transferrequest rather than a CPU interrupt instead. When the DMA has completed the transfer, itInterruptsMWCT101xS Series Reference Manual, Rev. 3, 07/20191078 NXP Semiconductors
