41.5.29.3 Update of the RegistersAfter writing new value to the registers with write buffer, selecting which of them will beupdated (according to Table 41-22), selecting the reload opportunities, selecting thefrequency of the reload opportunities, thus the LDOK bit should be set to enable theupdate of these registers at the next reload point.Table 41-22. Additional conditions to update the registersRegister Additional ConditionCNTIN CNTINC = 1HCR -MOD -C(n)V and C(n+1)V SYNCENm = 1, where m is the pair of the channels (n) and (n+1)41.5.30 Global LoadThe global load mechanism allows several modules to have their double bufferedregisters synchronously reloaded after a synchronization event if a write to one operationis performed in the global load OK (GLDOK) bit in the PWMLOAD register. Globalload may be enabled or disabled configuring the global load enable (GLEN) bit in thePWMLOAD register. Writing one in the GLDOK bit with GLEN enabled has the sameeffect of writing one in the LDOK bit. Refer to SoC specific information about globalload connections.Global load mechanism allows MOD, HCR, CNTIN, and C(n)V registers to be updatedwith the content of the register buffer at configurable reload point. The figure belowshows an example of connection between FTM global load inputs and outputsconsidering that GLDOK bit is implemented outside from FTM module.ftm_global_ldok_in ftm_global_ldok_inFTM module AFTM B or other peripheralGLEN bitLocal LDOKlogicGLDOK bitLocal LDOKset (internal)LDOK bitLocal LDOK logicLDOK bitFigure 41-112. Global load logicChapter 41 FlexTimer Module (FTM)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1275
