5. Configure the peripheral pins mux and features in the Port Control and Interruptsregister (PORTx_PCRn).6. Start communication10.1.4 Digital input filter configuration sequence1. Configure digital pin filtering controls for the corresponding pin usingPORTx_DFCR and PORTx_DFWR2. Enable PORTx_DFER[DFE]3. Configure PORTx_PCRn[MUX] for GPIO mode4. Wait for delay equivalent to PORTx_DFWR for filter enabling glitches to propagate5. Enable the corresponding function of the pin by configuring PORTx_PCRn[MUX]10.1.4.1 Digital input filter configuration sequence while using GPIOinterrupt1. Configure digital pin filtering controls for the corresponding pin usingPORTx_DFCR and PORTx_DFWR2. Enable PORTx_DFER[DFE]3. Configure PORTx_PCRn[MUX] for GPIO mode4. Wait for delay equivalent to PORTx_DFWR for filter enabling glitches to propagate5. Enable the interrupton the corresponding pin by configuring PORTx_PCRn[IRQC]10.1.4.2 Digital input filter configuration sequence while using NMI1. Configure digital pin filtering controls for the corresponding pin usingPORTD_DFCR and PORTD_DFWR2. Enable PORTD_DFER[3]3. Configure PORTD_PCR3[MUX] for GPIO mode4. Wait for delay equivalent to PORTD_DFWR for filter enabling glitches to propagate5. Configure the pin for NMI mode using PORTD_PCR3[MUX]Before entering STOP/VLPS modes, filter clock should be configured asLPO128K_CLK and reconfigured on wakeup, if required.If filtering is not required in STOP/VLPS modes, filtering should be disabled usingPORTx_DFER and reconfigured on wakeup, if required. If filtering is not required inSTOP/VLPS modes and is required wakeup onwards without reconfiguringPORTx_DFER (with bus clock as filter clock), it should be ensured that:cycles_tISR >> (PORTx_DFWR+3)*(SCG_xCCR[DIVBUS]+1)Chapter 10 Port Control and Interrupts (PORT)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 161
