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NXP Semiconductors MWCT1016SF Series manuals

MWCT1016SF Series first page preview

MWCT1016SF Series

Table of contents
  1. Table Of Contents
  2. Table Of Contents
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  31. Table Of Contents
  32. Table Of Contents
  33. Table Of Contents
  34. Table Of Contents
  35. Table Of Contents
  36. Table Of Contents
  37. Table Of Contents
  38. Table Of Contents
  39. Table Of Contents
  40. Audience
  41. Example: chip-specific information that clarifies content in the same chapter
  42. Example: chip-specific information that refers to a different chapter
  43. Register descriptions
  44. Conventions
  45. Typographic notation
  46. Overview
  47. Feature summary
  48. Block diagram
  49. Feature comparison
  50. Applications
  51. System modules
  52. Memories and memory interfaces
  53. Power Management
  54. Timer modules
  55. Communication interfaces
  56. Introduction
  57. Peripheral bridge (AIPS-Lite) memory map
  58. Read-after-write sequence and required serialization of memory operations
  59. Private Peripheral Bus (PPB) memory map
  60. Pad description
  61. Default pad state
  62. Signal Multiplexing sheet
  63. Input muxing table
  64. Pinout diagrams
  65. Cryptographic Services Engine (CSEc) security features
  66. Chain of trust: check flash memory for integrity and authenticity
  67. Secure communication
  68. Component protection
  69. Message-authentication example
  70. Steps required before failure analysis
  71. Security programming flow example (Secure Boot)
  72. WCT101xS safety concept
  73. Cortex-M4 Structural Core Self Test (SCST)
  74. Clock monitoring
  75. Diversity of system resources
  76. Arm Cortex-M4F core configuration
  77. Buses, interconnects, and interfaces
  78. Debug facilities
  79. Nested Vectored Interrupt Controller (NVIC) Configuration
  80. Non-maskable interrupt
  81. Asynchronous Wake-up Interrupt Controller (AWIC) Configuration
  82. FPU configuration
  83. JTAG controller configuration
  84. Chip-specific MCM information
  85. Memory map/register descriptions
  86. Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
  87. Core Platform Control Register (MCM_CPCR)
  88. Interrupt Status and Control Register (MCM_ISCR)
  89. Process ID Register (MCM_PID)
  90. Compute Operation Control Register (MCM_CPO)
  91. Local Memory Descriptor Register (MCM_LMDRn)
  92. Local Memory Descriptor Register2 (MCM_LMDR2)
  93. LMEM Parity and ECC Control Register (MCM_LMPECR)
  94. LMEM Fault Address Register (MCM_LMFAR)
  95. LMEM Fault Attribute Register (MCM_LMFATR)
  96. LMEM Fault Data High Register (MCM_LMFDHR)
  97. Functional description
  98. Chip-specific SIM information
  99. Memory map and register definition
  100. Chip-specific PORT information
  101. Number of PCRs
  102. Digital input filter configuration sequence
  103. Reset pin configuration
  104. Modes of operation
  105. External signal description
  106. Pin Control Register n (PORTx_PCRn)
  107. Global Pin Control Low Register (PORTx_GPCLR)
  108. Global Interrupt Control Low Register (PORTx_GICLR)
  109. Interrupt Status Flag Register (PORTx_ISFR)
  110. Digital Filter Clock Register (PORTx_DFCR)
  111. Global pin control
  112. External interrupts
  113. Chip-specific GPIO information
  114. GPIO register reset values
  115. GPIO signal descriptions
  116. Chip-specific AXBS-Lite information
  117. Arbitration
  118. Initialization/application information
  119. Chip-specific MPU information
  120. MPU Logical Bus Master Assignments
  121. Features
  122. MPU Memory map
  123. Control/Error Status Register (CESR)
  124. Error Address Register, slave port n (EAR0 - EAR4)
  125. Error Detail Register, slave port n (EDR0 - EDR4)
  126. Region Descriptor 0, Word 1 (RGD0_WORD1)
  127. Region Descriptor 0, Word 2 (RGD0_WORD2)
  128. Region Descriptor 0, Word 3 (RGD0_WORD3)
  129. Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)
  130. Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)
  131. Region Descriptor Alternate Access Control 0 (RGDAAC0)
  132. Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)
  133. Putting it all together and error terminations
  134. Chip-specific AIPS information
  135. Memory map/register definition
  136. Chip-specific DMAMUX information
  137. DMA channels with no triggering capability
  138. Chip-specific eDMA information
  139. eDMA system block diagram
  140. TCD initialization
  141. Fault reporting and handling
  142. Channel preemption
  143. Programming errors
  144. Arbitration mode considerations
  145. Monitoring transfer descriptor status
  146. Channel Linking
  147. Dynamic programming
  148. Suspend/resume a DMA channel with active hardware service requests
  149. Chip-specific TRGMUX information
  150. Chip-specific TRGMUX registers
  151. Chip-specific EWM information
  152. EWM_OUT_b pin state in low power modes
  153. EWM Counter
  154. EWM Interrupt
  155. Chip-specific EIM information
  156. EIM Memory map
  157. Error Injection Channel Enable register (EICHEN)
  158. Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)
  159. Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)
  160. Error injection scenarios
  161. Chip-specific ERM information
  162. ERM Configuration Register 0 (CR0)
  163. ERM Status Register 0 (SR0)
  164. ERM Memory n Error Address Register (EAR0 - EAR1)
  165. Non-correctable error events
  166. Initialization
  167. Chip-specific WDOG information
  168. Default watchdog timeout
  169. Watchdog refresh mechanism
  170. Configuring the Watchdog
  171. Using interrupts to delay resets
  172. Functionality in debug and low-power modes
  173. Application Information
  174. Configure Watchdog
  175. Chip-specific CRC information
  176. Transpose feature
  177. CRC result complement
  178. Power-on reset (POR)
  179. MCU Resets
  180. Reset pin
  181. Boot
  182. Boot sequence
  183. Chip-specific RCM information
  184. Reset memory map and register descriptions
  185. Parameter Register (RCM_PARAM)
  186. System Reset Status Register (RCM_SRS)
  187. Reset Pin Control register (RCM_RPC)
  188. Sticky System Reset Status Register (RCM_SSRS)
  189. System Reset Interrupt Enable Register (RCM_SRIE)
  190. Clock definitions
  191. Internal clocking requirements
  192. Clock divider values after reset
  193. Clock Gating
  194. Chip-specific SCG information
  195. Oscillator and SPLL guidelines
  196. Version ID Register (SCG_VERID)
  197. Parameter Register (SCG_PARAM)
  198. Clock Status Register (SCG_CSR)
  199. Run Clock Control Register (SCG_RCCR)
  200. VLPR Clock Control Register (SCG_VCCR)
  201. HSRUN Clock Control Register (SCG_HCCR)
  202. SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG)
  203. System OSC Control Status Register (SCG_SOSCCSR)
  204. System OSC Divide Register (SCG_SOSCDIV)
  205. System Oscillator Configuration Register (SCG_SOSCCFG)
  206. Slow IRC Control Status Register (SCG_SIRCCSR)
  207. Slow IRC Divide Register (SCG_SIRCDIV)
  208. Slow IRC Configuration Register (SCG_SIRCCFG)
  209. Fast IRC Control Status Register (SCG_FIRCCSR)
  210. Fast IRC Divide Register (SCG_FIRCDIV)
  211. Fast IRC Configuration Register (SCG_FIRCCFG)
  212. System PLL Control Status Register (SCG_SPLLCSR)
  213. System PLL Divide Register (SCG_SPLLDIV)
  214. System PLL Configuration Register (SCG_SPLLCFG)
  215. Chip-specific PCC information
  216. PCC FTFC Register (PCC_FTFC)
  217. PCC DMAMUX Register (PCC_DMAMUX)
  218. PCC FlexCAN0 Register (PCC_FlexCAN0)
  219. PCC FlexCAN1 Register (PCC_FlexCAN1)
  220. PCC FTM3 Register (PCC_FTM3)
  221. PCC ADC1 Register (PCC_ADC1)
  222. PCC FlexCAN2 Register (PCC_FlexCAN2)
  223. PCC LPSPI0 Register (PCC_LPSPI0)
  224. PCC LPSPI1 Register (PCC_LPSPI1)
  225. PCC LPSPI2 Register (PCC_LPSPI2)
  226. PCC PDB1 Register (PCC_PDB1)
  227. PCC CRC Register (PCC_CRC)
  228. PCC PDB0 Register (PCC_PDB0)
  229. PCC LPIT Register (PCC_LPIT)
  230. PCC FTM0 Register (PCC_FTM0)
  231. PCC FTM1 Register (PCC_FTM1)
  232. PCC FTM2 Register (PCC_FTM2)
  233. PCC ADC0 Register (PCC_ADC0)
  234. PCC RTC Register (PCC_RTC)
  235. PCC LPTMR0 Register (PCC_LPTMR0)
  236. PCC PORTA Register (PCC_PORTA)
  237. PCC PORTB Register (PCC_PORTB)
  238. PCC PORTC Register (PCC_PORTC)
  239. PCC PORTD Register (PCC_PORTD)
  240. PCC PORTE Register (PCC_PORTE)
  241. PCC FlexIO Register (PCC_FlexIO)
  242. PCC EWM Register (PCC_EWM)
  243. PCC LPI2C0 Register (PCC_LPI2C0)
  244. PCC LPI2C1 Register (PCC_LPI2C1)
  245. PCC LPUART0 Register (PCC_LPUART0)
  246. PCC LPUART1 Register (PCC_LPUART1)
  247. PCC LPUART2 Register (PCC_LPUART2)
  248. PCC FTM4 Register (PCC_FTM4)
  249. PCC FTM5 Register (PCC_FTM5)
  250. PCC FTM6 Register (PCC_FTM6)
  251. PCC FTM7 Register (PCC_FTM7)
  252. PCC CMP0 Register (PCC_CMP0)
  253. PCC QSPI Register (PCC_QSPI)
  254. SRAM sizes
  255. SRAM accessibility
  256. SRAM arbitration and priority control
  257. Chip-specific LMEM information
  258. Cache features
  259. SRAM Function
  260. Cache Function
  261. Cache Control
  262. Chip-specific MSCM information
  263. MSCM Memory Map/Register Definition
  264. Chip-specific FMC information
  265. FMC masters
  266. Default configuration
  267. Initialization and application information
  268. Chip-specific FTFC information
  269. Flash memory types
  270. Flash memory map
  271. Flash memory security
  272. Simultaneous operations on PFLASH read partitions
  273. Program flash 0 IFR map
  274. FlexNVM description
  275. Interrupts
  276. Flash operation in low-power modes
  277. Read while write (RWW)
  278. FTFC command operations
  279. Margin read commands
  280. Flash command descriptions
  281. Security
  282. Cryptographic Services Engine (CSEc)
  283. Reset sequence
  284. Chip-specific QuadSPI information
  285. Use case
  286. External memory options
  287. Recommended programming sequence
  288. QuadSPI_SOCCR[SOCCFG] implementation
  289. QuadSPI Modes of Operation
  290. Acronyms and Abbreviations
  291. Glossary for QuadSPI module
  292. Driving External Signals
  293. Peripheral Bus Register Descriptions
  294. Serial Flash Address Assignment
  295. Flash memory mapped AMBA bus
  296. AHB Bus Access Considerations
  297. Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B
  298. AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31)
  299. Interrupt Signals
  300. HyperRAM Support
  301. Flash Device Selection
  302. Byte Ordering - Endianness
  303. Programming Flash Data
  304. Reading Flash Data into the AHB Buffer
  305. Driving Flash Control Signals in Single and Dual Mode
  306. Sampling of Serial Flash Input Data
  307. Supported read modes
  308. Data Strobe (DQS) sampling method
  309. Data Input Hold Requirement of Flash
  310. Entering and exiting power modes
  311. Clocking modes
  312. Compute Operation (CPO)
  313. Peripheral Doze
  314. Power mode transitions
  315. Shutdown sequencing for power modes
  316. QuadSPI operation
  317. Memory map and register descriptions
  318. SMC Parameter Register (SMC_PARAM)
  319. Power Mode Protection register (SMC_PMPROT)
  320. Power Mode Control register (SMC_PMCTRL)
  321. Stop Control Register (SMC_STOPCTRL)
  322. Power Mode Status register (SMC_PMSTAT)
  323. Power mode entry/exit sequencing
  324. Run modes
  325. Stop modes
  326. Debug in low power modes
  327. Chip-specific PMC information
  328. Low Voltage Reset (LVR) Operation
  329. PMC register descriptions
  330. Instantiation information
  331. ADC Connections/Channel Assignment
  332. DMA Support on ADC
  333. ADC internal supply monitoring
  334. ADC Trigger Sources
  335. PDB triggering scheme
  336. TRGMUX trigger scheme
  337. Trigger Latching and Arbitration
  338. ADC triggering configurations
  339. ADC low-power modes
  340. ADC calibration scheme
  341. Chip-specific ADC information
  342. ADC signal descriptions
  343. Analog Channel Inputs (ADx)
  344. ADC Status and Control Register 1 (SC1A - aSC1P)
  345. ADC Configuration Register 1 (CFG1)
  346. ADC Configuration Register 2 (CFG2)
  347. ADC Data Result Registers (RA - aRP)
  348. Compare Value Registers (CV1 - CV2)
  349. Status and Control Register 2 (SC2)
  350. Status and Control Register 3 (SC3)
  351. BASE Offset Register (BASE_OFS)
  352. ADC Offset Correction Register (OFS)
  353. USER Offset Correction Register (USR_OFS)
  354. ADC X Offset Correction Register (XOFS)
  355. ADC Y Offset Correction Register (YOFS)
  356. ADC Gain Register (G)
  357. ADC User Gain Register (UG)
  358. ADC General Calibration Value Register S (CLPS)
  359. ADC Plus-Side General Calibration Value Register 3 (CLP3)
  360. ADC Plus-Side General Calibration Value Register 2 (CLP2)
  361. ADC Plus-Side General Calibration Value Register 0 (CLP0)
  362. ADC Plus-Side General Calibration Value Register X (CLPX)
  363. ADC Plus-Side General Calibration Value Register 9 (CLP9)
  364. ADC General Calibration Offset Value Register S (CLPS_OFS)
  365. ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS)
  366. ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS)
  367. ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS)
  368. ADC Plus-Side General Calibration Offset Value Register 0 (CLP0_OFS)
  369. ADC Plus-Side General Calibration Offset Value Register X (CLPX_OFS)
  370. ADC Plus-Side General Calibration Offset Value Register 9 (CLP9_OFS)
  371. ADC Status and Control Register 1 (SC1AA - SC1Z)
  372. ADC Data Result Registers (RAA - RZ)
  373. Voltage reference selection
  374. Conversion control
  375. Automatic compare function
  376. Calibration function
  377. User-defined offset function
  378. MCU Normal Stop mode operation
  379. Chip-specific CMP information
  380. CMP external references
  381. CMP trigger mode
  382. bit DAC key features
  383. CMP block diagram
  384. CMP pin descriptions
  385. CMP functional modes
  386. Disabled mode (# 1)
  387. Continuous mode (#s 2A & 2B)
  388. Sampled, Filtered mode (#s 4A & 4B)
  389. Windowed mode (#s 5A & 5B)
  390. Windowed/Filtered mode (#7)
  391. Memory map/register definitions
  392. CMP Control Register 1 (CMPx_C1)
  393. CMP Control Register 2 (CMPx_C2)
  394. CMP functional description
  395. Low-pass filter
  396. DAC functional description
  397. DAC clocks
  398. Chip-specific PDB information
  399. PDB trigger interconnections with ADC and TRGMUX
  400. Pulse-Out Enable Register Implementation
  401. Implementation
  402. Status and Control register (PDBx_SC)
  403. Modulus register (PDBx_MOD)
  404. Interrupt Delay register (PDBx_IDLY)
  405. Channel n Status register (PDBx_CHnS)
  406. Channel n Delay 0 register (PDBx_CHnDLY0)
  407. Channel n Delay 1 register (PDBx_CHnDLY1)
  408. Channel n Delay 3 register (PDBx_CHnDLY3)
  409. Channel n Delay 4 register (PDBx_CHnDLY4)
  410. Channel n Delay 6 register (PDBx_CHnDLY6)
  411. Channel n Delay 7 register (PDBx_CHnDLY7)
  412. Pulse-Out n Delay register (PDBx_POnDLY)
  413. PDB trigger input source selection
  414. Updating the delay registers
  415. Impact of using the prescaler and multiplication factor on timing resolution
  416. Chip-specific FTM information
  417. FTM Interrupts
  418. FTM Hardware Triggers and Synchronization
  419. FTM Input Capture Options
  420. FTM Modulation Implementation
  421. FTM Global Time Base
  422. FTM signal descriptions
  423. Prescaler
  424. Channel Modes
  425. Input Capture Mode
  426. Output Compare mode
  427. Edge-Aligned PWM (EPWM) mode
  428. Center-Aligned PWM (CPWM) mode
  429. Combine mode
  430. Modified Combine PWM Mode
  431. Complementary Mode
  432. Registers updated from write buffers
  433. PWM synchronization
  434. Inverting
  435. Software Output Control Mode
  436. Deadtime insertion
  437. Output mask
  438. Fault Control
  439. Polarity Control
  440. External Trigger
  441. Initialization Trigger
  442. Capture Test Mode
  443. Dual Edge Capture Mode
  444. Quadrature Decoder Mode
  445. Debug mode
  446. Reload Points
  447. Global Load
  448. Global time base (GTB)
  449. Channel trigger output
  450. External Control of Channels Output
  451. Reset Overview
  452. Initialization Procedure
  453. Chip-specific LPIT information
  454. LPIT input triggers
  455. Memory Map and Registers
  456. Timer Modes
  457. Channel Chaining
  458. Detailed timing
  459. Chip-specific LPTMR information
  460. LPTMR signal descriptions
  461. LPTMR register descriptions
  462. LPTMR prescaler/glitch filter
  463. LPTMR counter
  464. LPTMR compare
  465. Chip-specific RTC information
  466. Multiple trigger
  467. Register definition
  468. Time counter
  469. Compensation
  470. Time alarm
  471. Interrupt
  472. Chip-specific LPSPI information
  473. Signal Descriptions
  474. Master Mode
  475. Slave Mode
  476. Interrupts and DMA Requests
  477. Peripheral Triggers
  478. Chip-specific LPI2C information
  479. LPI2C register descriptions
  480. Clocking and Resets
  481. Chip-specific LPUART information
  482. Baud rate generation
  483. Receiver functional description
  484. Additional LPUART functions
  485. Infrared interface
  486. Interrupts and status flags
  487. Chip-specific FlexIO information
  488. Shifter operation
  489. Timer Operation
  490. Pin operation
  491. UART Receive
  492. SPI Master
  493. SPI Slave
  494. I2C Master
  495. I2S Master
  496. I2S Slave
  497. Chip-specific FlexCAN information
  498. FlexCAN external time tick
  499. FlexCAN oscillator clock
  500. FlexCAN signal descriptions
  501. CAN register descriptions
  502. FlexCAN memory partition for CAN FD
  503. FlexCAN message buffer memory map
  504. Rx FIFO structure
  505. Arbitration process
  506. Receive process
  507. Matching process
  508. Receive process under Pretended Networking mode
  509. Move process
  510. Data coherence
  511. Rx FIFO
  512. CAN protocol related features
  513. Clock domains and restrictions
  514. Modes of operation details
  515. Bus interface
  516. CM4 ROM table
  517. Debug port
  518. Debug port pin descriptions
  519. MDM-AP status and control registers
  520. MDM-AP Control Register
  521. MDM-AP Status Register
  522. Debug resets
  523. AHB-AP
  524. Core trace connectivity
  525. Debug in low-power modes
  526. Debug module state in low-power modes
  527. Chip-specific JTAGC information
  528. Test mode select (TMS)
  529. Device identification register
  530. Boundary scan register
  531. TAP controller state machine
  532. JTAGC block instructions
  533. Boundary scan
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