NXP Semiconductors MWCT1016SF Series manuals
MWCT1016SF Series
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Audience
- Example: chip-specific information that clarifies content in the same chapter
- Example: chip-specific information that refers to a different chapter
- Register descriptions
- Conventions
- Typographic notation
- Overview
- Feature summary
- Block diagram
- Feature comparison
- Applications
- System modules
- Memories and memory interfaces
- Power Management
- Timer modules
- Communication interfaces
- Introduction
- Peripheral bridge (AIPS-Lite) memory map
- Read-after-write sequence and required serialization of memory operations
- Private Peripheral Bus (PPB) memory map
- Pad description
- Default pad state
- Signal Multiplexing sheet
- Input muxing table
- Pinout diagrams
- Cryptographic Services Engine (CSEc) security features
- Chain of trust: check flash memory for integrity and authenticity
- Secure communication
- Component protection
- Message-authentication example
- Steps required before failure analysis
- Security programming flow example (Secure Boot)
- WCT101xS safety concept
- Cortex-M4 Structural Core Self Test (SCST)
- Clock monitoring
- Diversity of system resources
- Arm Cortex-M4F core configuration
- Buses, interconnects, and interfaces
- Debug facilities
- Nested Vectored Interrupt Controller (NVIC) Configuration
- Non-maskable interrupt
- Asynchronous Wake-up Interrupt Controller (AWIC) Configuration
- FPU configuration
- JTAG controller configuration
- Chip-specific MCM information
- Memory map/register descriptions
- Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
- Core Platform Control Register (MCM_CPCR)
- Interrupt Status and Control Register (MCM_ISCR)
- Process ID Register (MCM_PID)
- Compute Operation Control Register (MCM_CPO)
- Local Memory Descriptor Register (MCM_LMDRn)
- Local Memory Descriptor Register2 (MCM_LMDR2)
- LMEM Parity and ECC Control Register (MCM_LMPECR)
- LMEM Fault Address Register (MCM_LMFAR)
- LMEM Fault Attribute Register (MCM_LMFATR)
- LMEM Fault Data High Register (MCM_LMFDHR)
- Functional description
- Chip-specific SIM information
- Memory map and register definition
- Chip-specific PORT information
- Number of PCRs
- Digital input filter configuration sequence
- Reset pin configuration
- Modes of operation
- External signal description
- Pin Control Register n (PORTx_PCRn)
- Global Pin Control Low Register (PORTx_GPCLR)
- Global Interrupt Control Low Register (PORTx_GICLR)
- Interrupt Status Flag Register (PORTx_ISFR)
- Digital Filter Clock Register (PORTx_DFCR)
- Global pin control
- External interrupts
- Chip-specific GPIO information
- GPIO register reset values
- GPIO signal descriptions
- Chip-specific AXBS-Lite information
- Arbitration
- Initialization/application information
- Chip-specific MPU information
- MPU Logical Bus Master Assignments
- Features
- MPU Memory map
- Control/Error Status Register (CESR)
- Error Address Register, slave port n (EAR0 - EAR4)
- Error Detail Register, slave port n (EDR0 - EDR4)
- Region Descriptor 0, Word 1 (RGD0_WORD1)
- Region Descriptor 0, Word 2 (RGD0_WORD2)
- Region Descriptor 0, Word 3 (RGD0_WORD3)
- Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)
- Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)
- Region Descriptor Alternate Access Control 0 (RGDAAC0)
- Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)
- Putting it all together and error terminations
- Chip-specific AIPS information
- Memory map/register definition
- Chip-specific DMAMUX information
- DMA channels with no triggering capability
- Chip-specific eDMA information
- eDMA system block diagram
- TCD initialization
- Fault reporting and handling
- Channel preemption
- Programming errors
- Arbitration mode considerations
- Monitoring transfer descriptor status
- Channel Linking
- Dynamic programming
- Suspend/resume a DMA channel with active hardware service requests
- Chip-specific TRGMUX information
- Chip-specific TRGMUX registers
- Chip-specific EWM information
- EWM_OUT_b pin state in low power modes
- EWM Counter
- EWM Interrupt
- Chip-specific EIM information
- EIM Memory map
- Error Injection Channel Enable register (EICHEN)
- Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)
- Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)
- Error injection scenarios
- Chip-specific ERM information
- ERM Configuration Register 0 (CR0)
- ERM Status Register 0 (SR0)
- ERM Memory n Error Address Register (EAR0 - EAR1)
- Non-correctable error events
- Initialization
- Chip-specific WDOG information
- Default watchdog timeout
- Watchdog refresh mechanism
- Configuring the Watchdog
- Using interrupts to delay resets
- Functionality in debug and low-power modes
- Application Information
- Configure Watchdog
- Chip-specific CRC information
- Transpose feature
- CRC result complement
- Power-on reset (POR)
- MCU Resets
- Reset pin
- Boot
- Boot sequence
- Chip-specific RCM information
- Reset memory map and register descriptions
- Parameter Register (RCM_PARAM)
- System Reset Status Register (RCM_SRS)
- Reset Pin Control register (RCM_RPC)
- Sticky System Reset Status Register (RCM_SSRS)
- System Reset Interrupt Enable Register (RCM_SRIE)
- Clock definitions
- Internal clocking requirements
- Clock divider values after reset
- Clock Gating
- Chip-specific SCG information
- Oscillator and SPLL guidelines
- Version ID Register (SCG_VERID)
- Parameter Register (SCG_PARAM)
- Clock Status Register (SCG_CSR)
- Run Clock Control Register (SCG_RCCR)
- VLPR Clock Control Register (SCG_VCCR)
- HSRUN Clock Control Register (SCG_HCCR)
- SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG)
- System OSC Control Status Register (SCG_SOSCCSR)
- System OSC Divide Register (SCG_SOSCDIV)
- System Oscillator Configuration Register (SCG_SOSCCFG)
- Slow IRC Control Status Register (SCG_SIRCCSR)
- Slow IRC Divide Register (SCG_SIRCDIV)
- Slow IRC Configuration Register (SCG_SIRCCFG)
- Fast IRC Control Status Register (SCG_FIRCCSR)
- Fast IRC Divide Register (SCG_FIRCDIV)
- Fast IRC Configuration Register (SCG_FIRCCFG)
- System PLL Control Status Register (SCG_SPLLCSR)
- System PLL Divide Register (SCG_SPLLDIV)
- System PLL Configuration Register (SCG_SPLLCFG)
- Chip-specific PCC information
- PCC FTFC Register (PCC_FTFC)
- PCC DMAMUX Register (PCC_DMAMUX)
- PCC FlexCAN0 Register (PCC_FlexCAN0)
- PCC FlexCAN1 Register (PCC_FlexCAN1)
- PCC FTM3 Register (PCC_FTM3)
- PCC ADC1 Register (PCC_ADC1)
- PCC FlexCAN2 Register (PCC_FlexCAN2)
- PCC LPSPI0 Register (PCC_LPSPI0)
- PCC LPSPI1 Register (PCC_LPSPI1)
- PCC LPSPI2 Register (PCC_LPSPI2)
- PCC PDB1 Register (PCC_PDB1)
- PCC CRC Register (PCC_CRC)
- PCC PDB0 Register (PCC_PDB0)
- PCC LPIT Register (PCC_LPIT)
- PCC FTM0 Register (PCC_FTM0)
- PCC FTM1 Register (PCC_FTM1)
- PCC FTM2 Register (PCC_FTM2)
- PCC ADC0 Register (PCC_ADC0)
- PCC RTC Register (PCC_RTC)
- PCC LPTMR0 Register (PCC_LPTMR0)
- PCC PORTA Register (PCC_PORTA)
- PCC PORTB Register (PCC_PORTB)
- PCC PORTC Register (PCC_PORTC)
- PCC PORTD Register (PCC_PORTD)
- PCC PORTE Register (PCC_PORTE)
- PCC FlexIO Register (PCC_FlexIO)
- PCC EWM Register (PCC_EWM)
- PCC LPI2C0 Register (PCC_LPI2C0)
- PCC LPI2C1 Register (PCC_LPI2C1)
- PCC LPUART0 Register (PCC_LPUART0)
- PCC LPUART1 Register (PCC_LPUART1)
- PCC LPUART2 Register (PCC_LPUART2)
- PCC FTM4 Register (PCC_FTM4)
- PCC FTM5 Register (PCC_FTM5)
- PCC FTM6 Register (PCC_FTM6)
- PCC FTM7 Register (PCC_FTM7)
- PCC CMP0 Register (PCC_CMP0)
- PCC QSPI Register (PCC_QSPI)
- SRAM sizes
- SRAM accessibility
- SRAM arbitration and priority control
- Chip-specific LMEM information
- Cache features
- SRAM Function
- Cache Function
- Cache Control
- Chip-specific MSCM information
- MSCM Memory Map/Register Definition
- Chip-specific FMC information
- FMC masters
- Default configuration
- Initialization and application information
- Chip-specific FTFC information
- Flash memory types
- Flash memory map
- Flash memory security
- Simultaneous operations on PFLASH read partitions
- Program flash 0 IFR map
- FlexNVM description
- Interrupts
- Flash operation in low-power modes
- Read while write (RWW)
- FTFC command operations
- Margin read commands
- Flash command descriptions
- Security
- Cryptographic Services Engine (CSEc)
- Reset sequence
- Chip-specific QuadSPI information
- Use case
- External memory options
- Recommended programming sequence
- QuadSPI_SOCCR[SOCCFG] implementation
- QuadSPI Modes of Operation
- Acronyms and Abbreviations
- Glossary for QuadSPI module
- Driving External Signals
- Peripheral Bus Register Descriptions
- Serial Flash Address Assignment
- Flash memory mapped AMBA bus
- AHB Bus Access Considerations
- Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B
- AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31)
- Interrupt Signals
- HyperRAM Support
- Flash Device Selection
- Byte Ordering - Endianness
- Programming Flash Data
- Reading Flash Data into the AHB Buffer
- Driving Flash Control Signals in Single and Dual Mode
- Sampling of Serial Flash Input Data
- Supported read modes
- Data Strobe (DQS) sampling method
- Data Input Hold Requirement of Flash
- Entering and exiting power modes
- Clocking modes
- Compute Operation (CPO)
- Peripheral Doze
- Power mode transitions
- Shutdown sequencing for power modes
- QuadSPI operation
- Memory map and register descriptions
- SMC Parameter Register (SMC_PARAM)
- Power Mode Protection register (SMC_PMPROT)
- Power Mode Control register (SMC_PMCTRL)
- Stop Control Register (SMC_STOPCTRL)
- Power Mode Status register (SMC_PMSTAT)
- Power mode entry/exit sequencing
- Run modes
- Stop modes
- Debug in low power modes
- Chip-specific PMC information
- Low Voltage Reset (LVR) Operation
- PMC register descriptions
- Instantiation information
- ADC Connections/Channel Assignment
- DMA Support on ADC
- ADC internal supply monitoring
- ADC Trigger Sources
- PDB triggering scheme
- TRGMUX trigger scheme
- Trigger Latching and Arbitration
- ADC triggering configurations
- ADC low-power modes
- ADC calibration scheme
- Chip-specific ADC information
- ADC signal descriptions
- Analog Channel Inputs (ADx)
- ADC Status and Control Register 1 (SC1A - aSC1P)
- ADC Configuration Register 1 (CFG1)
- ADC Configuration Register 2 (CFG2)
- ADC Data Result Registers (RA - aRP)
- Compare Value Registers (CV1 - CV2)
- Status and Control Register 2 (SC2)
- Status and Control Register 3 (SC3)
- BASE Offset Register (BASE_OFS)
- ADC Offset Correction Register (OFS)
- USER Offset Correction Register (USR_OFS)
- ADC X Offset Correction Register (XOFS)
- ADC Y Offset Correction Register (YOFS)
- ADC Gain Register (G)
- ADC User Gain Register (UG)
- ADC General Calibration Value Register S (CLPS)
- ADC Plus-Side General Calibration Value Register 3 (CLP3)
- ADC Plus-Side General Calibration Value Register 2 (CLP2)
- ADC Plus-Side General Calibration Value Register 0 (CLP0)
- ADC Plus-Side General Calibration Value Register X (CLPX)
- ADC Plus-Side General Calibration Value Register 9 (CLP9)
- ADC General Calibration Offset Value Register S (CLPS_OFS)
- ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS)
- ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS)
- ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS)
- ADC Plus-Side General Calibration Offset Value Register 0 (CLP0_OFS)
- ADC Plus-Side General Calibration Offset Value Register X (CLPX_OFS)
- ADC Plus-Side General Calibration Offset Value Register 9 (CLP9_OFS)
- ADC Status and Control Register 1 (SC1AA - SC1Z)
- ADC Data Result Registers (RAA - RZ)
- Voltage reference selection
- Conversion control
- Automatic compare function
- Calibration function
- User-defined offset function
- MCU Normal Stop mode operation
- Chip-specific CMP information
- CMP external references
- CMP trigger mode
- bit DAC key features
- CMP block diagram
- CMP pin descriptions
- CMP functional modes
- Disabled mode (# 1)
- Continuous mode (#s 2A & 2B)
- Sampled, Filtered mode (#s 4A & 4B)
- Windowed mode (#s 5A & 5B)
- Windowed/Filtered mode (#7)
- Memory map/register definitions
- CMP Control Register 1 (CMPx_C1)
- CMP Control Register 2 (CMPx_C2)
- CMP functional description
- Low-pass filter
- DAC functional description
- DAC clocks
- Chip-specific PDB information
- PDB trigger interconnections with ADC and TRGMUX
- Pulse-Out Enable Register Implementation
- Implementation
- Status and Control register (PDBx_SC)
- Modulus register (PDBx_MOD)
- Interrupt Delay register (PDBx_IDLY)
- Channel n Status register (PDBx_CHnS)
- Channel n Delay 0 register (PDBx_CHnDLY0)
- Channel n Delay 1 register (PDBx_CHnDLY1)
- Channel n Delay 3 register (PDBx_CHnDLY3)
- Channel n Delay 4 register (PDBx_CHnDLY4)
- Channel n Delay 6 register (PDBx_CHnDLY6)
- Channel n Delay 7 register (PDBx_CHnDLY7)
- Pulse-Out n Delay register (PDBx_POnDLY)
- PDB trigger input source selection
- Updating the delay registers
- Impact of using the prescaler and multiplication factor on timing resolution
- Chip-specific FTM information
- FTM Interrupts
- FTM Hardware Triggers and Synchronization
- FTM Input Capture Options
- FTM Modulation Implementation
- FTM Global Time Base
- FTM signal descriptions
- Prescaler
- Channel Modes
- Input Capture Mode
- Output Compare mode
- Edge-Aligned PWM (EPWM) mode
- Center-Aligned PWM (CPWM) mode
- Combine mode
- Modified Combine PWM Mode
- Complementary Mode
- Registers updated from write buffers
- PWM synchronization
- Inverting
- Software Output Control Mode
- Deadtime insertion
- Output mask
- Fault Control
- Polarity Control
- External Trigger
- Initialization Trigger
- Capture Test Mode
- Dual Edge Capture Mode
- Quadrature Decoder Mode
- Debug mode
- Reload Points
- Global Load
- Global time base (GTB)
- Channel trigger output
- External Control of Channels Output
- Reset Overview
- Initialization Procedure
- Chip-specific LPIT information
- LPIT input triggers
- Memory Map and Registers
- Timer Modes
- Channel Chaining
- Detailed timing
- Chip-specific LPTMR information
- LPTMR signal descriptions
- LPTMR register descriptions
- LPTMR prescaler/glitch filter
- LPTMR counter
- LPTMR compare
- Chip-specific RTC information
- Multiple trigger
- Register definition
- Time counter
- Compensation
- Time alarm
- Interrupt
- Chip-specific LPSPI information
- Signal Descriptions
- Master Mode
- Slave Mode
- Interrupts and DMA Requests
- Peripheral Triggers
- Chip-specific LPI2C information
- LPI2C register descriptions
- Clocking and Resets
- Chip-specific LPUART information
- Baud rate generation
- Receiver functional description
- Additional LPUART functions
- Infrared interface
- Interrupts and status flags
- Chip-specific FlexIO information
- Shifter operation
- Timer Operation
- Pin operation
- UART Receive
- SPI Master
- SPI Slave
- I2C Master
- I2S Master
- I2S Slave
- Chip-specific FlexCAN information
- FlexCAN external time tick
- FlexCAN oscillator clock
- FlexCAN signal descriptions
- CAN register descriptions
- FlexCAN memory partition for CAN FD
- FlexCAN message buffer memory map
- Rx FIFO structure
- Arbitration process
- Receive process
- Matching process
- Receive process under Pretended Networking mode
- Move process
- Data coherence
- Rx FIFO
- CAN protocol related features
- Clock domains and restrictions
- Modes of operation details
- Bus interface
- CM4 ROM table
- Debug port
- Debug port pin descriptions
- MDM-AP status and control registers
- MDM-AP Control Register
- MDM-AP Status Register
- Debug resets
- AHB-AP
- Core trace connectivity
- Debug in low-power modes
- Debug module state in low-power modes
- Chip-specific JTAGC information
- Test mode select (TMS)
- Device identification register
- Boundary scan register
- TAP controller state machine
- JTAGC block instructions
- Boundary scan
manualsdatabase
Your AI-powered manual search engine