Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)MPC5566 Microcontroller Reference Manual, Rev. 211-22 Freescale Semiconductor11.4.2 Clock Operation11.4.2.1 Input Clock FrequencyThe FMPLL is designed to operate over an input clock frequency range as determined by the operatingmode. The operating ranges for each mode are given in Table 11-7.11.4.2.2 Reduced Frequency Divider (RFD)The RFD can be used for reducing the FMPLL system clock frequency. To protect the system fromfrequency overshoot during the PLL lock detect phase, the RFD must be programmed to be greater thanor equal to 1 when changing MFD or PREDIV or when enabling frequency modulation.11.4.2.3 Programmable Frequency ModulationThe FMPLL provides for frequency modulation of the system clock. The modulation is applied as atriangular waveform with modulation depth and rate controlled by fields in the FMPLL_SYNCR. Themodulation depth can be set to ±1% or ±2% of the system frequency. The modulation rate is dependent onthe reference clock frequency.Complete details for configuring the programmable frequency modulation is given in Section 11.4.3.2,“Programming System Clock Frequency with Frequency Modulation.”11.4.2.4 FMPLL Lock DetectionA pair of counters monitor the reference and feedback clocks to determine when the system has acquiredfrequency lock. After the FMPLL has locked, the counters continue to monitor the reference and feedbackclocks and reports if/when the FMPLL has lost lock. The FMPLL_SYNCR provides the flexibility toselect whether to generate an interrupt, assert system reset, or do nothing in the event that the FMPLL loseslock. Refer to Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR) for details.When the frequency modulation is enabled, the loss of lock continues to function as described but with thelock and loss of lock criteria reduced to ensure that false loss of lock conditions are not detected.In bypass mode, the FMPLL cannot lock since the FMPLL is disabled.11.4.2.5 FMPLL Loss-of-Lock ConditionsAfter the FMPLL acquires lock after reset, the FMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS]status bits are set. If the MFD is changed or if an unexpected loss of lock condition occurs, the LOCK andTable 11-7. Input Clock FrequencyMode Symbol Input Frequency RangeCrystal referenceExternal referenceFref_crystalFref_ext8–20 MHzBypass Fextal 0–132 MHzDual-controller (1:1) Fref_1:1 25–66 MHz
