System Integration Unit (SIU)MPC5566 Microcontroller Reference Manual, Rev. 26-16 Freescale SemiconductorThe following table describes the fields in the external interrupt status register:6.3.1.5 DMA Interrupt Request Enable Register (SIU_DIRER)The SIU_DIRER asserts a DMA transfer or external interrupt request if the IRQ flag bit is set in theSIU_EISR. The DMA transfer or external interrupt request enable bits (EIRE flags) enable an externalinterrupt request or DMA transfer request. The SIU uses one interrupt request to the interrupt controller.The EIRE bits determine the external interrupt requests that assert the SIU interrupt request to the interruptcontroller.Address: Base + 0x0014 Access: R/w1c0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R EIF15 EIF14 EIF13 EIF12 EIF11 EIF10 EIF9 EIF8 EIF7 EIF6 EIF5 EIF4 EIF3 EIF2 EIF1 EIF0W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 6-5. External Interrupt Status Register (SIU_EISR)Table 6-11. SIU_EISR Field DescriptionsField Description0–15 Reserved16–31EIFnExternal interrupt request flag n. This bit is set when an edge-triggered event occurs on the corresponding IRQ[n]input. Cleared by writing a 1.0 No edge-triggered event has occurred on the corresponding IRQ[n] input.1 An edge-triggered event has occurred on the corresponding IRQ[n] input.Address: Base + 0x0018 Access: R/W0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R EIRE15EIRE14EIRE13EIRE12EIRE11EIRE10EIRE9EIRE8EIRE7EIRE6EIRE5EIRE4EIRE3EIRE2EIRE1EIRE0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 6-6. DMA Interrupt Request Enable Register (SIU_DIRER)
