Enhanced Serial Communication Interface (eSCI)MPC5566 Microcontroller Reference Manual, Rev. 221-20 Freescale Semiconductor21.4.3 Baud Rate GenerationA 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and thetransmitter. The value, 1 to 8191, written to the SBR0–SBR12 bits determines the system clock divider.The SBR bits are in the eSCI control register 1 (ESCIx_CR1). The baud rate clock is synchronized withthe system clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. Thereceiver has an acquisition rate of 16 samples per bit time.Baud rate generation is subject to one source of error when integer division of the system clock does notresult in the exact target frequency.Table 21-17 lists some examples of achieving target baud rates with a system clock frequency of 128 MHz.Table 21-17. Baud Rates (Example: System Clock = 128 MHz)BitsSBR[0:12]ReceiverClock (Hz)TransmitterClock (Hz)Target BaudRateError(%)0x0023 3,657,143 228,571 230,400 –0.790x0045 1,855,072 115,942 115,200 +0.640x008B 920,863 57,554 57,600 –0.010x00D0 615,385 38,462 38,400 +0.160x01A1 306,954 19,185 19,200 –0.080x022C 230,216 14,388 14,400 –0.080x0341 153,661 9,604 9600 +.040x0683 76,785 4,799 4800 –0.020x0D05 38,404 2,400.2 2400 +.010x1A0A 19,202 1,200.1 1200 +.01SCI baud rate System clock16 ESCIx_CR1[SBR]×-------------------------------------------------------------=
