External Bus Interface (EBI)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 12-912.2.1.8 Transfer Acknowledge (TA)TA is asserted to indicate that the slave device has received the data (and completed the access) for a writecycle, or returned data for a read cycle. If the transaction is a burst read, TA is asserted for each one of thetransaction beats. For write transactions, TA is only asserted once at access completion, even if more thanone write data beat is transferred.TA is driven by the EBI when the access is controlled by the chip selects or when an external masterinitiates the transaction to an internal module. Otherwise, TA is driven by the slave device to which thecurrent transaction was addressed.During a calibration bus access, TA is held negated.See Section 12.4.2.9, “Termination Signals Protocol” for more details.12.2.1.9 Transfer Error Acknowledge (TEA)In the 416 BGA package and 496 assembly, TEA is asserted by either the EBI or an external device toindicate that an error condition has occurred during the bus cycle. TEA assertion terminates the cycleimmediately, overriding the value of the TA signal.TEA is asserted by the EBI when the internal bus monitor detected a timeout error, or when an externalmaster initiated a transaction to an internal module and an internal error was detected.The VertiCal assembly supports the TEA signal.During a calibration bus access, TEA is held negated.See Section 12.4.2.9, “Termination Signals Protocol” for more details.12.2.1.10 Transfer Start (TS)TS is asserted by the current bus owner to indicate the start of a transaction on the external bus.TS is driven by the EBI or an external master depending on the module that controls the external bus. TSis only asserted for the first clock cycle of the transaction, and is negated in the successive clock cyclesuntil the end of the transaction.During a calibration bus access, TS is held negated.12.2.1.11 Write/Byte Enables (WE/BE)Write enables are used to enable program operations to a particular memory. These signals can also be usedas byte enables for read and write operation by setting the WEBS bit in the appropriate base register.The WE/BE signals are only asserted for chip select accesses.The WE/BE signals are driven by the EBI or an external master depending on the module that controls theexternal bus.The VertiCal assembly and the 416 BGA package use WE/BE[0:3].During a calibration bus access, the WE/BE signals are held negated.
