Deserial Serial Peripheral Interface (DSPI)MPC5566 Microcontroller Reference Manual, Rev. 220-54 Freescale Semiconductor20.4.6.3 After SCK Delay (t ASC)The after SCKx delay is the length of time between the last edge of SCKx and the negation of PCSx. SeeFigure 20-34 and Figure 20-35 for illustrations of the after SCKx delay. The PASC and ASC fields in theDSPIx_CTARn registers select the after SCK delay. The relationship between these variables is given inthe following formula:Table 20-25 shows an example of the computed after SCK delay.20.4.6.4 Delay after Transfer (t DT)The delay-after-transfer field is the amount of time between negation of the PCSx signal for a frame andthe assertion of the PCSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registersselect the delay after transfer.See Figure 20-34 for an illustration of the delay after transfer. The following formula expresses the PDTand DT delay-after-transfer relationship:Table 20-26 shows an example of the computed delay after transfer.20.4.6.5 Peripheral Chip Select Strobe Enable (PCSS)The PCSS signal provides a delay to allow the PCSx signals to settle after transitioning thereby avoidingglitches. When the DSPI is in master mode and PCSSE bit is set in the DSPIx_MCR, PCSS provides asignal for an external demultiplexer to decode the PCSx[0:4] signals into as many as 32 glitch-free PCSxsignals.Table 20-25. After SCK Delay Computation ExamplePASC PrescalerValue ASC ScalerValue fSYS After SCK Delay0b01 3 0b0100 32 100 MHz 0.96 μsTable 20-26. Delay after Transfer Computation ExamplePDT PrescalerValue DT ScalerValue fSYS Delay after Transfer0b01 3 0b1110 32768 100 MHz 0.98 mstASC = f SYSASC× PASC1 ×tDT = fSYSDT× PDT1 ×
