External Bus Interface (EBI)MPC5566 Microcontroller Reference Manual, Rev. 212-26 Freescale SemiconductorNOTEDue to testing and complexity concerns, multi-master (or master/slave)operation between an MPC55xx and MPC5xx is not guaranteed.12.4.1.18 Misaligned Access SupportThe EBI supports misaligned non-burst chip-select transfers only from internal masters. The EBI alignsthe accesses when it transmits data to the external bus (splitting them into multiple-aligned accesses) toconnect external devices that only support aligned accesses. Burst accesses (internal master) must be32-bit aligned.12.4.1.18.1 Misaligned Access Support (32-bit)Table 12-14 shows the misaligned access cases supported by a 32-bit implementation, as detected on theinternal master bus. No support is available for all other misaligned access cases. If a misaligned accessoccurs that is not supported (such as a non-chip-select or misaligned burst access), the EBI generates amisaligned access error on the internal bus and does not start the access (nor assert TEA) externally.Table 12-15 shows which external transfers are generated by the EBI for the misaligned access cases inTable 12-14, for each port size.The number of external transfers for each internal AHB master request is determined by the HSIZE valuefor that request relative to the port size. For example, a halfword write to 0×0003 (misaligned case #4) with16-bit port size results in four external 16-bit transfers because of the transfer granularity of 32 bits. ForTable 12-14. Misalignment Cases Supported by a 32-bit Internal EBICaseNumbers 11 This is the misaligned case number. Only transfers where HUNALIGN = 1 are numbered as misaligned cases.All other case numbers for byte misalignment do not apply to a 32-bit EBI implementation.Program SizeandByte OffsetAddress[30:31] 2, 32 The address on internal master AHB bus is not necessarily the address on external ADDR pins.3 The addresses with a ‘z’ increment an additional 32-bit word compared to the previous AHB access.Data Bus Byte Strobes 44 Internal byte strobe signals.Port Size(HSIZE 5)5 Internal signal on the AHB bus: 00 = 8 bits; 01 = 16 bits; 10 = 32 bits. HSIZE uses the smallest aligned container that has allthe requested bytes, which can result in extra EBI external transfers.Byte Alignment(HUNALIGN)External busbig-endianAHB buslittle-endian1 Half-word @ 0x0001 01 0110 0110 10 = 32 bits 1 = Misaligned4 Half-word @ 0x0003(two AHB transfers)11z00000110001000000101 = 16 bits 600 = 8 bits6 The EBI internally treats this case as if HSIZE = 00 (1-byte access).1 = Misaligned0 = Aligned8 Word @ 0x0001(two AHB transfers) 01 011110001110000110 = 32 bits00 = 8 bits1 = Misaligned0 = Aligned9 Word @ 0x0002(two AHB transfers) 10 001111001100001110 = 32 bits01 = 16 bits1 = Misaligned0 = Aligned1011Word @ 0x0003(two AHB transfers)11z00000111101000011110 = 32 bits 610 = 32 bits1 = Misaligned1 = Misaligned
