Enhanced Time Processing Unit (eTPU)MPC5566 Microcontroller Reference Manual, Rev. 218-14 Freescale SemiconductorThe output disable channel groups are defined in Table 18-3.18.4 Memory Map and Register Definition18.4.1 eTPU Memory Map OverviewThe eTPU system simplified memory map is shown in Table 18-4. The base address for the eTPU moduleis listed as BASE. Each of the register areas shown can have their own reserved address areas.Table 18-3. Output Disable Channel GroupseMIOS Channel Engine eTPU Channels Disabled11A0–710 8–159 16–238 24–3120B0–721 8–1522 16–2323 24–31Table 18-4. eTPU High-Level Memory MapAddress Register DescriptionBase (C3FC_0000)–Base + 0x0000_001F eTPU system module configuration registersBase + (0x0000_0020–0x0000_002F) eTPU A time base registersBase + (0x0000_0030–0x0000_003F) ReservedBase + (0x0000_0040–0x0000_004F) eTPU B time base registersBase + (0x0000_0050–0x0000_01FF) ReservedBase + (0x0000_0200–0x0000_02FF) eTPU A and B global channel registersBase + (0x0000_0300–0x0000_03FF) ReservedBase + (0x0000_0400–0x0000_07FF) eTPU A channel registersBase + (0x0000_0800–0x0000_0BFF) eTPU B channel registersBase + (0x0000_0C00–0x0000_7FFF) ReservedBase + (0x0000_8000–0x0000_8FFF) Shared data memory (4 KB)Base + (0x0000_9000–0x0000_BFFF) ReservedBase + (0x0000_C000–0x0000_CFFF) Shared data memory PSE mirror1 (4 KB)Base + (0x0000_CD00–0x0000_FFFF) Reserved
