Error Correction Status Module (ECSM)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 8-38.2.1 Register DescriptionsAttempted accesses to reserved addresses result in an error termination, while attempted writes toread-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to theprogramming model must match the size of the register; for example, an n-bit register only supports n-bitwrites, etc. Attempted writes of a different size than the register width produce an error termination of thebus cycle and no change to the targeted register.8.2.1.1 Software Watchdog Timer Control, Service, and Interrupt Registers(ECSM_SWTCR, ECSM_SWTSR, and ECSM_SWTIR)These registers provide control and configuration for a software watchdog timer, and are included as partof a standard Freescale ECSM module incorporated in the device. The e200z6 core also provides thisfunctionality and is the preferred method for watchdog implementation. To optimize code portability toother Power Architecture-based products in the MPC5500 family, use the e200z6 watchdog functionsinstead of the registers in the ECSM.NOTEDo not change the reset values in the ECSM watchdog registers. Anychange to the reset values can cause an unintentionalECSM_SWTIR_SWTIC interrupt.8.2.1.2 ECC RegistersThere are a number of program-visible registers for the sole purpose of reporting and logging of memoryfailures. These registers include the following:• ECC configuration register (ECSM_ECR)• ECC status register (ECSM_ESR)• ECC error generation register (EEGR)• Flash ECC address register (ECSM_FEAR)• Flash ECC master number register (ECSM_FEMR)• Flash ECC attributes register (ECSM_FEAT)• Flash ECC data register (ECSM_FEDR)• RAM ECC address register (ECSM_REAR)• RAM ECC master number register (ECSM_REMR)• RAM ECC attributes register (ECSM_REAT)• RAM ECC data register (ECSM_REDR)The details of each ECC register are in the subsequent sections.
