MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 18-1Chapter 18Enhanced Time Processing Unit (eTPU)18.1 IntroductionThe enhanced time processing unit (eTPU) operates in parallel with the MPC5566 core (CPU) to:• Execute programs independently from the host core• Detect and precisely record the timing of input events• Generate complex output waveforms• Enhances the CPU with time processing without requiring real-time host processingThe host core setup and service times for each input and output event are greatly minimized. TheMPC5566 contains two eTPUs.The eTPU improves the performance of the device by providing high-resolution timing:• eTPU dedicated channels include two match and two capture registers (TPUs had one).• eTPU engines are optimized to service channel hardware• Fast instruction execution rate of the eTPU engine reduces service timeBecause responding to hardware service requests is primarily done by the eTPU engine, the host is free tohandle higher level operations.18.1.1 eTPU ImplementationFor more detailed information regarding the eTPU module and compiler, refer to the Enhanced TimeProcessing (eTPU) Reference Manual. This chapter provides an overview of the eTPU module:• 4 KB of shared data memory (SDM). This memory is also referred to as eTPU shared parameter(SP) RAM, or (SPRAM).• 20 KB of shared code memory (SCM).• MPC5566 has two eTPU engines: eTPU A and eTPU B• The eTPU debug interface is built into the device’s debug module. Refer to Section 10.2.1 of theeTPU Reference Manual for details on eTPU debug.• Data transfer requests are implemented to each eTPU engine: eTPU A has five DMA requests;eTPU B has 12 DMA requests.• I/O channel pairs can be shared on a common pin. The output buffer enable (OBE) is not used inthe device. The outputs are enabled in the SIU; refer to Chapter 6, “System Integration Unit (SIU).”
