Deserial Serial Peripheral Interface (DSPI)MPC5566 Microcontroller Reference Manual, Rev. 220-42 Freescale Semiconductor20.4.4.4 DSI DeserializationWhen all bits in a DSI frame have been shifted in, the frame is copied to the DSPIx_DDR. This registerpresents the deserialized data as parallel output signal values. The DSPIx_DDR is memory mapped toallow host software to read the deserialized data directly. Figure 20-20 shows the DSI deserialization logic.for more information on the DSPIx_DDR.See Section 20.3.2.14, “DSPI DSI Deserialization Data Register (DSPIx_DDR).”Figure 20-20. DSI Deserialization Diagram20.4.4.5 DSI Transfer Initiation ControlData transfers for a master DSPI in DSI configuration are initiated by a condition. When chaining DSPIs,the master and all slaves must be configured for the transfer initiation. The transfer initiation conditionsare selected by the TRRE and CID bits in the DSPIx_DSICR.Table 20-18 lists the four transfer initiation conditions.20.4.4.5.1 Continuous ControlFor continuous control, the initiation of a transfer is based on the baud rate at which data is transferredbetween the DSPI and the external device. The baud rate is set in the DSPIx_CTAR selected by theDSICTAS field in the DSPIx_DSICR. A new DSI frame shifts out when the previous transfer cycle hascompleted and the delay after transfer (tDT) has elapsed.Table 20-18. DSI Data Transfer Initiation ControlDSPIx_DSICR BitsType of Transfer Initiation ControlTRRE CID0 0 Continuous0 1 Change in data1 0 Triggered1 1 Triggered or change in dataSINControllogic0 1 • • • • • 15Shift register16Slave bus interfaceParallelDSI deserializationdata register outputs16
