Enhanced Queued Analog-to-Digital Converter (eQADC)MPC5566 Microcontroller Reference Manual, Rev. 219-16 Freescale Semiconductor19.3.2.4 eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn)The EQADC_CFPRs provide a mechanism to fill the CFIFOs with command messages from the commandqueues. Refer to Section 19.4.3, “eQADC Command FIFOs,” for more information on the CFIFOs and toSection 19.4.1.2, “Message Format in eQADC,” for a description on command message formats.0b1011 2049 17075.000b1100 4097 34141.670b1101 8193 68275.000b1110 16385 136541.670b1111 32769 273075.00Address: Base + 0x0010 (EQADC_CFPR0)Base + 0x0014 (EQADC_CFPR1);Base + 0x0018 (EQADC_CFPR2)Base + 0x001C (EQADC_CFPR3)Base + 0x0020 (EQADC_CFPR4)Base + 0x0024 (EQADC_CFPR5)Access: WO0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0W CF_PUSHnReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0W CF_PUSHnReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 19-5. eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn)Table 19-7. EQADC_CFPRn Field DescriptionsField Description0–31CF_PUSHn[0:31]CFIFO push data n. When CFIFOn is not full, writing to the whole word or any bytes of EQADC_CFPRn pushesthe 32-bit CF_PUSHn value into CFIFOn. Writing to the CF_PUSHn field also increments the correspondingCFCTRn value by one in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn).”When the CFIFOn is full, the eQADC ignores any write to the CF_PUSHn. Reading the EQADC_CFPRn alwaysreturns 0.Note: Write only whole words to the EQADC_CFPRn registers. Writing halfwords or bytes to EQADC_CFPRpushes the entire 32-bit CF_PUSH field into the CFIFO, but undefined data fills the areas of CF_PUSH thatwere not specifically designated as target locations for the write.Table 19-6. Minimum Required Time to Valid ETRIG (continued)DFL[0:3] Minimum Clock Count Minimum Time (ns)(System Clock = 120MHz)
