IntroductionMPC5566 Microcontroller Reference Manual, Rev. 21-18 Freescale Semiconductorserialization and deserialization of eTPU channels, eMIOS channels and memory-mapped registers. Thechannels and register content are transmitted using a SPI-like protocol.The MPC5566 has four DSPI modules (A, B, C, and D). The DSPIs have three configurations:• Serial peripheral interface (SPI) configuration where the DSPIs operate as serial ports only withsupport for queues.• Deserial serial interface (DSI) configuration where the DSPIs serialize eTPU and eMIOS outputchannels, and deserialize the input data by passing it to the eTPU and eMIOS input channels.• Combined serial interface (CSI) configuration where the DSPIs operate in both SPI and DSIconfigurations, interleaving DSI frames with SPI frames, and giving priority to SPI frames.For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfersbetween the memory and the DSPI FIFOs use the eDMA controller or the host software.1.5.17 Enhanced Serial Communications Interface (eSCI)The enhanced serial communications interface (eSCI) allows asynchronous serial communications withperipheral devices and other MCUs. It includes special support to interface to local interconnect network(LIN) slave devices. The MPC5566 has two eSCI modules (A and B).1.5.18 Flexible Controller Area Network (FlexCAN)The MCU contains four controller area network (FlexCAN) modules. Each FlexCAN module is acommunication controller implementing the CAN protocol according to CAN Specification version 2.0B.The CAN protocol is designed to be used primarily as a vehicle serial data bus, meeting the specificrequirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle,cost-effectiveness, and required bandwidth. Each FlexCAN module contains 64 message buffers.1.5.19 Nexus Development Interface (NDI)The Nexus development interface (NDI) module provides real-time development support capabilities forthe MPC5500 family’s MCU built on the Power Architecture in compliance with the IEEE®-ISTO5001-2003 standard. This development support is supplied for MCUs without requiring external addressand data pins for internal visibility. The NDI module integrates several Nexus modules to provide thedevelopment support interface for the MPC5500 family. The NDI module interfaces to the host processor,single or dual eTPU processors, and internal buses to provide development support as per theIEEE®-ISTO 5001-2003 standard. The development support provided includes program trace, data trace,watchpoint trace, ownership trace, run-time access to the MCU internal memory map, Nexus trace ofeDMA transfers, and access to the Power Architecture and eTPU internal registers during a halt, using theauxiliary port. The Nexus interface also supports a JTAG only mode using only the JTAG pins.1.5.20 JTAG Controller (JTAGC)The JTAG controller (JTAGC) module provides the means to test chip functionality and connectivity whileremaining transparent to system logic when not in test mode. Testing is performed via a boundary scantechnique, as defined in the IEEE® 1149.1-2001 standard. All data input to and output from the JTAGC
