Flash MemoryMPC5566 Microcontroller Reference Manual, Rev. 213-34 Freescale Semiconductor13.4.2.5 Flash Shadow BlockThe flash shadow block is a memory-mapped block in the flash memory map. Program and erase of theshadow block are enabled only when FLASH_MCR[PEAS] = 1. After the user has begun an eraseoperation on the shadow block, the operation cannot be suspended to program the main address space andvice-versa. The user must terminate the shadow erase operation to program or erase the main addressspace.NOTEIf an erase of user space is requested, and a suspend is done with attemptsto erase suspend program shadow space, this attempted program is directedto user space as dictated by the state of FLASH_MCR[PEAS]. Likewise anattempted erase suspended program of user space, while the shadow spaceis being erased, is directed to shadow space as dictated by the state ofFLASH_MCR[PEAS].The shadow block cannot utilize the RWW feature. After an operation is started in the shadow block, aread cannot be done to the shadow block, or any other block. Likewise, after an operation is started in ablock in low/mid/high address space, a read cannot be done in the shadow block.The shadow block contains information on how the lock registers are reset. The first and second words canbe used for reset configuration words. All other words can be used for user defined functions or otherconfiguration words.The shadow block can be locked/unlocked against program or erase by using the FLASH_LMLR orFLASH_SLMLR discussed in Section 13.3.2, “Register Descriptions.”Programming of the shadow row has similar restrictions to programming the array in terms of how ECCis calculated. Refer to Section 13.4.2.3, “Flash Programming” for more information. Only one program isallowed per 64 bit ECC segment between erases. Erase of the shadow row is done similarly as an arrayerase. Refer to Section 13.4.2.4, “Flash Erase” for more information.13.4.2.6 CensorshipCensorship logic disables access to internal flash based on the censorship control word value and theBOOTCFG[0:1] bits in the SIU_RSR. This prevents modification of the FLASH_BIUAPR bitfieldsassociated with all masters except the core based on the censorship control word value, theBOOTCFG[0:1] bits in the SIU_RSR, and the EXTM bit in the EBI_MCR. Also, censorship logic sets theboot default value to external-with-external-master access disabled based on the value of the censorshipcontrol word and a TCU input signal.13.4.2.6.1 Censorship Control WordThe censorship control word is a 32-bit value located at the base address of the shadow row plus 0x1E0.The flash module latches the value of the control word prior to the negation of system reset. Censorshiplogic uses the value latched in the flash module to disable access to internal flash, disable the NDI, preventmodification of the FLASH_BIUAPR bitfields, and/or set the boot default value.
