e200z6 Core ComplexMPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 3-233.3.2.1 Cache OrganizationThe e200z6 cache is organized as 4 or 8 ways of 128 sets with each line containing 32 bytes (fourdoublewords) plus parity of storage. Figure 3-14 illustrates the cache organization, terminology used, thecache line format, and cache tag formats.Figure 3-14. Cache Organization and Line Format3.3.2.2 Cache LookupAfter it is enabled, the unified cache is searched for a tag match on all instruction fetches and data accessesfrom the CPU. If a match is found, the cached data is forwarded on a read access to the instruction fetchunit or the load/store unit (data access), or is updated on a write access, and can also be written-through tomemory if required.When a read miss occurs, if there is a TLB hit and the cache inhibit bit (WIMGE=0bx0xxx) of the hittingTLB entry is clear, the translated physical address is used to fetch a four doubleword cache line beginningwith the requested doubleword (critical doubleword first). The line is fetched and placed into theappropriate cache block and the critical doubleword is forwarded to the CPU. Subsequent doublewordscan be streamed to the CPU if they have been requested and streaming is enabled via the DSTRM bit inthe L1CSR0 register.During a cache line fill, doublewords received from the bus are placed into a cache linefill buffer, and canbe forwarded (streamed) to the CPU if such a request is pending. Accesses from the CPU followingdelivery of the critical doubleword can be satisfied from the cache (hit under fill, non-blocking) or fromthe linefill buffer if the requested information has been already received.The cache always fills an entire line, thereby providing validity on a line-by-line basis. A cache line isalways in one of the following states: invalid, valid, or dirty (and valid). For invalid lines, the V bit is clear,causing the cache line to be ignored during lookups. Valid lines have their V bit set and D bit cleared,Way 0 Way 1 Way 2 Way 7Line••••••••••••VDTagCache line formatDoubleword 3Doubleword 2Doubleword 1Doubleword 0Set 0Set 1Set 126Set 127•••LA[0:19]Tag address TagVDvalidLLinelockLinedirty• • • •Cache tag formatPParitybitsP
