CalibrationMPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor B-5The drive strength of the calibration pins is configured in the PCR registers. In some cases, multiple padshave their drive strengths controlled by one PCR by grouping the pins:• CAL_ADDR[12:30]• CAL_DATA[0:15]• CAL_RD_WR, CAL_WE/BE[0:1], CAL_OE, CAL_TSThe SIU_PCR registers control whether the CAL_CS[2:3] pins are used for CAL_CS[2:3] or forCAL_ADDR[10:11]. Refer to Table B-2 for the pin assignments. Selecting between CAL_CS[2:3] andCAL_ADDR[10:11] allows you to maximize the amount of calibration memory size by limiting thenumber of calibration chip selects to CS[0]. Refer to Section B.4.1.1, “Number of Chip Selects andMaximum Memory Size.”B.4.3 CLKOUTCLKOUT is supplied by the clock control block, not the EBI. Nevertheless, the same CLKOUT is usedfor both the non-calibration and calibration bus.A drawback of having just one CLKOUT is that while the difference in board timing can be compensatedby the adjustment in the drive strength, the CLKOUT timing, and hence the timing of the non-calibrationbus, can have minor differences with a calibration tool from the production package.B.5 PackagingThe addition of the calibration bus means that the device has more pads than can be connected to the ballson a 416 pin package. Therefore, the die is assembled in a 496 pin chip scale package (CSP) and thispackage is used in the VertiCal base assembly.B.6 Power SuppliesThe signals that make up the calibration bus have their own power supply segment (VDDE12). The V DDE12power supply balls are not connected to any other power supply segment from the standard packageball-out but are routed on the VertiCal base to pins on the VertiCal connector. The VertiCal top board mustprovide voltage to the VDDE12 power supply pins to power up the calibration bus.B.7 Integration Logic FunctionalityThe EBI connects to both the non-calibration and calibration buses. The integration logic on MPC5566selects between the data input from both buses to the EBI.The MPC5566 integration logic also suppresses the reflections of the outputs of the calibration bus ontothe non-calibration bus. For the non-calibration bus pins that do not have a negated state to which the pinsreturn at the end of the access, this reflection suppression is enabled by the SIU_CCR[CRSE] bit.SIU_CCR[CRSE] does not enable reflection suppression for the non-calibration bus pins that have anegated state to which the pins return at the end of an access. Those reflections always are suppressed.Furthermore, the suppression of reflections from the non-calibration bus onto the calibration bus is notenabled by CRSE. Those reflections are also always suppressed.
