MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 13-1Chapter 13Flash Memory13.1 IntroductionThis section provides information about the flash bus interface unit (FBIU) and the flash memory block.13.1.1 Block DiagramFigure 13-1 shows a block diagram of the flash memory module. The FBIU is addressed through thesystem bus while the flash control and status registers are addressed through the slave (peripheral) bus.Figure 13-1. Flash System Block Diagram13.1.2 OverviewThe flash module serves as electrically programmable and erasable non-volatile memory (NVM) that isideal for program and data storage for single-chip applications allowing for field reprogramming withoutrequiring external programming voltage sources. The module is a solid-state silicon memory deviceconsisting of blocks of single-transistor storage elements.The device flash contains a flash bus interface unit (FBIU) and a flash memory array. The Flash BIUinterfaces the system bus to a dedicated flash memory array controller. The FBIU supports a 64-bit databus width at the system bus port, and a 256-bit read data interface from the flash memory array. If enabled,the Flash BIU contains a two-entry prefetch buffer, each entry containing 256 bits of data, and anassociated controller that prefetches sequential lines of data from the flash array into the buffer. PrefetchFlash businterfaceunit(FBIU)Flash memoryFlash memory blockFlash coreControl andregistersinterface(MI)VFLASHVSS VDD VPPSlavebusSystembusstatus
