Deserial Serial Peripheral Interface (DSPI)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 20-5920.4.7.3 Modified Transfer Format Enabled (MTFE = 1) withClassic SPI Transfer Format Cleared (CPHA = 0) for SPI and DSIIn the modified transfer format, the master and the slave sample later in the SCK period than in classic SPImode to allow for delays in device pads and board traces. These delays become a more significant fractionof the SCK period as the SCK period decreases with increasing baud rates.NOTEFor the modified transfer format to operate correctly, you must thoroughlyanalyze the SPI link timing budget.The master and the slave send data to the SOUTx pins when the PCSx signal asserts. After the PCSx toSCKx delay elapses the first SCKx edge is generated. The slave samples the master SOUTx signal on everyodd numbered SCKx edge. The slave also sends more data on the slave SOUTx on every odd numberedclock edge.The master sends its second data bit to the SOUTx pin one system clock after the odd numbered SCKxedge. The master samples the slave SOUTx pins by writing to the SMPL_PT field in the DSPIx_MCR.Table 20-29 lists the number of system clock cycles (between the active-edge of SCKx and the mastersample point) for different values of the SMPL_PT bit field. The master sample point can be delayed byone or two system clock cycles.Table 20-29. Delayed Master Sample PointSMPL_PT Number of System Clock Cycles betweenOdd-numbered Edge of SCK and Sampling of SIN00 001 110 211 Invalid value
