Fast Ethernet Controller (FEC)MPC5566 Microcontroller Reference Manual, Rev. 215-44 Freescale Semiconductor15.4.14.2 Reception Errors15.4.14.2.1 Overrun ErrorIf the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OVbit in the RxBD. All subsequent data in the frame is discarded and subsequent frames can also be discardeduntil the receive FIFO is serviced by the DMA and space is made available. At this point the receiveframe/status word is written into the FIFO with the OV bit set. This frame must be discarded by the driver.15.4.14.2.2 Non-Octet Error (Dribbling Bits)The Ethernet controller handles up to seven dribbling bits when the receive frame terminates past annon-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error,then the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, then no erroris reported.15.4.14.2.3 CRC ErrorWhen a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the RxBD.CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required.15.4.14.2.4 Frame Length ViolationWhen the receive frame length exceeds MAX_FL bytes, the BABR interrupt is generated, and the LG bitin the end of frame RxBD is set. The frame is not truncated unless the frame length exceeds 2047 bytes).15.4.14.2.5 TruncationWhen the receive frame length exceeds 2047 bytes the frame is truncated, and the TR bit is set in theRxBD.15.5 Buffer DescriptorsThis section provides a description of the operation of the driver/DMA via the buffer descriptors. It isfollowed by a detailed description of the receive and transmit descriptor fields.15.5.1 Driver/DMA Operation with Buffer DescriptorsThe data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed inone or more buffers. Associated with each buffer is a buffer descriptor (BD) which contains a startingaddress (pointer), data length, and status/control information (which contains the current state for thebuffer). To permit maximum flexibility, the BDs are also located in external memory and are read in bythe FEC DMA engine.Software “produces” buffers by allocating/initializing memory and initializing buffer descriptors. Settingthe RxBD[E] or TxBD[R] bit “produces” the buffer. Software writing to either the TDAR or RDAR tellsthe FEC that a buffer has been placed in external memory for the transmit or receive data traffic,respectively. The hardware reads the BDs and “consumes” the buffers after they have been produced. After
