MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 1-1Chapter 1Introduction1.1 OverviewThe MPC5566 microcontroller (MCU) is a member of the MPC5500 family of next generation powertrainmicrocontrollers built on Power Architecture™ technology. The MPC5500 family contains a hostprocessor core that complies with the Power Architecture embedded category, which is 100 percent usermode compatible with the original Power PC™ user instruction set architecture (UISA). This family ofparts contains many new features coupled with high-performance CMOS technology to provide significantperformance improvement over the MPC565.The e200z6 CPU of the MPC5500 family is part of the family of CPU cores that implement versions builton the Power Architecture embedded category. This core also has additional instructions, including digitalsignal processing (DSP) instructions, beyond the classic PowerPC instruction set.The MPC5566 has the following memory hierarchy:Unified cache 32 KB unified cacheSRAM 128 KB of internal SRAMFlash 3 MB flash memoryThe fastest accesses are to the unified cache.Both the internal SRAM and the flash memory holdinstructions and data. The external bus interface is designed to support most of the standard memories usedwith the MPC5xx family.The complex I/O timer functions of the MPC5500 family are performed by two enhanced time processorunit engines (eTPUs). Each eTPU engine controls 32 hardware channels. The eTPU has been enhancedover the TPU by providing 24-bit timers, double-action hardware channels, a variable number ofparameters per channel, angle clock hardware, and additional control and arithmetic instructions. EacheTPU is programmed using a high-level programming language.The timer functions of the MPC5500 family are performed by the enhanced modular input/output system(eMIOS). The eMIOS’ 24 hardware channels are capable of single action, double action, pulse-widthmodulation (PWM), and modulus counter operation. Motor control capabilities include edge-aligned andcenter-aligned PWM.Off-chip communication is performed by a suite of serial protocols including:• 4 controller area networks (FlexCANs);• 4 enhanced deserial/serial peripheral interface (DSPIs); and• 2 enhanced serial communications interfaces (eSCIs).
