Enhanced Direct Memory Access (eDMA)MPC5566 Microcontroller Reference Manual, Rev. 29-14 Freescale Semiconductorcomplete, disabling the DMA hardware request. Otherwise if the D_REQ bit is cleared, the state of theEDMA_ERQR bit is unaffected.9.2.2.4 eDMA Enable Error Interrupt Registers (EDMA_EEIRH, EDMA_EEIRL)The EDMA_EEIRH and EDMA_EEIRL provide a bit map for the 64 channels to enable the error interruptsignal for each channel.EDMA_EEIRH supports channels 63–32, while EDMA_EEIRL covers channels31–0.The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it isalso affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The EDMA_SEEIR andEDMA_CEEIR are provided so that the error interrupt enable for a single channel can easily be modifiedwithout the need to perform a read-modify-write sequence to the EDMA_EEIRH and EDMA_EEIRL.Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interruptrequest for a given channel is asserted.Address: Base + 0x0010 Access: User read/write0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R EEI63EEI62EEI61EEI60EEI59EEI58EEI57EEI56EEI55EEI54EEI53EEI52EEI51EEI50EEI49EEI48WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R EEI47EEI46EEI45EEI44EEI43EEI42EEI41EEI40EEI39EEI38EEI37EEI36EEI35EEI34EEI33EEI32WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 9-6. eDMA Enable Error Interrupt High Register (EDMA_EEIRH)Address: Base + 0x0014 Access: User R/W0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R EEI31EEI30EEI29EEI28EEI27EEI26EEI25EEI24EEI23EEI22EEI21EEI20EEI19EEI18EEI17EEI16WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R EEI15EEI14EEI13EEI12EEI11EEI10EEI09EEI08EEI07EEI06EEI05EEI04EEI03EEI02EEI01EEI00WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 9-7. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL)
