Interrupt Controller (INTC)MPC5566 Microcontroller Reference Manual, Rev. 210-30 Freescale SemiconductorThe lower vector is chosen regardless of the time order of the assertions of the peripheral or softwaresettable interrupt requests.10.4.2.1.3 Vector Encoder SubmoduleThe vector encoder submodule generates the unique 9-bit vector for the asserted interrupt request from therequest selector submodule.10.4.2.1.4 Priority Comparator SubmoduleThe priority comparator submodule compares the highest priority output from the priority arbitratorsubmodule with PRI in INTC_CPR. If the priority comparator submodule detects that this highest priorityis higher than the current priority, then it asserts the interrupt request to the processor. This interrupt requestto the processor asserts whether this highest priority is raised above the value of PRI in INTC_CPR or thePRI value in INTC_CPR is lowered below this highest priority. This highest priority then becomes the newpriority which is written to PRI in INTC_CPR when the interrupt request to the processor isacknowledged. Interrupt requests whose PRIn in INTC_PSRn are zero does not cause a preemptionbecause their PRIn is not higher than PRI in INTC_CPR.10.4.2.2 LIFOThe LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities arestacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interruptexception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR andstored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does notneed to be loaded from the context stack and stored into the INTC_CPR.The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in softwarevector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode.The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written.Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 is notpreempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only 14entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO andpopping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the prioritiesfirst pushed are overwritten. A priority of 0 is an overwritten priority. However, the LIFO pop zeros if itis popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is regeneratedwith the popping of an empty LIFO.The LIFO is not memory mapped.
