Interrupt Controller (INTC)MPC5566 Microcontroller Reference Manual, Rev. 210-4 Freescale Semiconductor• If the total number of available interrupts is a multiple of four, no additional interrupt vectors exist.In hardware vector mode, the core branches to an interrupt exception handler unique for each interruptrequest source. Typical program flow for hardware vector mode is shown in Figure 10-4.Figure 10-4. Program Flow–Hardware Vector ModeFor high priority interrupt requests in these target applications, the time from the assertion of the interruptrequest from the peripheral to when the processor is performing useful work to service the interrupt requestneeds to be minimized. The INTC can be optimized to support this goal through the hardware vector mode,where a unique vector is provided for each interrupt request source. It also provides 16 priorities so thatlower priority ISRs do not delay the execution of higher priority ISRs. Since each individual applicationhas different priorities for each source of interrupt request, the priority of each interrupt request isconfigurable.When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTCsupports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, thepriority level can be raised temporarily so that no task can preempt another task that shares the sameresource.Multiple processors can assert interrupt requests to each other through software settable interrupt requests,i.e., by using application software to assert an interrupt request. These same software settable interruptrequests also can be used to break the work involved in servicing an interrupt request into a high priorityportion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request,but then the ISR can assert a software settable interrupt request to finish the servicing in a lower priorityISR.10.1.3 FeaturesFeatures include the following:• Total number of interrupt vectors is 3321, of which:— 298 are peripheral interrupt vectors— 8 are software settable sourcesPrologb handler 0 handler 0ISR••••••ISR••••••InstructionsNOTE:‘b ISR_n’ is technicallyEpilogPrologEpilogISRPrologEpiloghandler nhandler Nb handler 1•••b handler 2•••b handler nb handler NIVPR + 0x0000IVPR + 0x0010IVPR + 0x0020IVPR + n [0x0010]Refer to definition of NIRQ[n]takenAddresspart of the handler.
