Interrupt Controller (INTC)MPC5566 Microcontroller Reference Manual, Rev. 210-28 Freescale SemiconductorNOTEThe peripheral or software settable interrupt request asserts when the PRInvalue in the interrupt priority select register (INTC_PSRn) is greater thanthe PRIn value in interrupt current priority register (INTC_CPR).If an asserted peripheral or software settable interrupt request negates beforethe processor acknowledges its request, the interrupt request can reassertand remain asserted. If this occurs, the processor uses the INTC_PSRn valueto locate the IRQ vector, and updates the PRIn value in the INTC_CPR withthe PRIn value in INTC_PSRn.Clearing the peripheral interrupt request enable bit for the peripheralinitiating the request, or setting the IRQ mask bit has the same consequencesas clearing its flag bit. Setting its enable bit or clearing its mask bit while itsflag bit is asserted has the same effect on the INTC as an interrupt eventsetting the flag bit.10.4.1.1 Peripheral Interrupt RequestsAn interrupt event in a peripheral’s hardware sets a flag bit which resides in that peripheral. The interruptrequest from the peripheral is driven by that flag bit.The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the timethat the INTC starts to drive the interrupt request to the processor is three clocks.10.4.1.2 Software Settable Interrupt RequestsThe software set/clear interrupt registers (INTC_SSCIRx_x) support the setting or clearing ofsoftware-settable interrupt requests. These registers contain eight independent sets of bits to set and cleara corresponding flag bit by software. With the exception of being set by software, this flag bit behaves thesame as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC justlike a peripheral interrupt request.An interrupt request is triggered by software writing a 1 to the SETn bit in INTC software set/clearinterrupt registers (INTC_SSCIR0–INTC_SSCIR7). This write sets a CLRn flag bit that generates an0x1480 328 CAND_IFRH[BUF63:BUF32] FlexCAN D buffers 63–32 interrupts0x1490–0x14B0 329–331 Reserved1 The vector number is used to identify the interrupt priority select register; it does not indicate the maximum number of usableinterrupt sources.2 Interrupt requests from the same module location are ORed together.Table 10-9. MPC5566 Interrupt Request Sources (continued)HardwareVector ModeOffsetVectorNumber 1 Source2 Description
