e200z6 Core ComplexMPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 3-33• Decrementer register (DEC)—a decrementing counter that is updated at the same rate as the timebase. The DEC provides a means of signaling an exception after a specified amount of time. TheDEC is typically used as a general-purpose software timer. Note that the decrementer always runswhen the system is clocked, and can be written to by software at any time.• Decrementer auto reload register (DECAR)—provides a value that is automatically reloaded (ifenabled) into the decrementer register when the decrementer reaches 0.For more information on the fixed-interval timer, watchdog timer, and timer and counter registers, refer tothe e200z6 PowerPCTM Core Reference Manual and EREF: A Programmer's Reference Manual forFreescale Book E Processors.3.3.6 Signal Processing Extension APU (SPE APU)The Power Architecture embedded category 32-bit instructions operate on the lower (least significant)32 bits of the 64-bit GPRs. New SPE instructions are defined that view the 64-bit register as beingcomposed of a vector of two 32-bit elements, and some of the instructions also read or write 16-bitelements. These new instructions can also be used to perform scalar operations by ignoring the results ofthe upper 32-bit half of the register file.Some instructions are defined that produce a 64-bit scalar result. Vector fixed-point instructions operateon a vector of two 32-bit or four 16-bit fixed-point numbers resident in the 64-bit GPRs. Vectorfloating-point instructions operate on a vector of two 32-bit single-precision floating-point numbersresident in the 64-bit GPRs. Scalar floating-point instructions operate on the lower half of GPRs. Thesesingle-precision floating-point instructions do not have a separate register file; there is a single sharedregister file for all instructions. Figure 3-18 shows two different representations of the 64-bit GPRs. Theshaded half is the only region operated on by the 32-bit Power Architecture embedded categoryinstructions.Figure 3-18. 64-bit General-Purpose Registers3.3.7 SPE Programming ModelNot all SPE instructions record events such as overflow, saturation, and negative/positive result. See thedescription of the individual SPE instruction in the e200z6 core reference for information on whichconditions are recorded and where they are recorded. Most SPE instructions record conditions to theSPEFSCR. Vector compare instructions store the result of the comparison into the condition register (CR).The e200z6 core has a 64-bit architectural accumulator register that holds the results of the SPE multiplyaccumulate (MAC) fixed-point instructions. The accumulator allows back-to-back execution of dependentfixed-point MAC instructions, something that is found in the inner loops of DSP code such as filters. The0 31 32 63GPRx Lower-least significant wordUpper-most significant word15 16 47 480 31 32 63GPRx
