Interrupt Controller (INTC)MPC5566 Microcontroller Reference Manual, Rev. 210-6 Freescale SemiconductorFigure 10-5. Software Vector Mode: Interrupt Exception Handler Address CalculationReading the INTC_IACKR acknowledges the INTC’s interrupt request and negates the interrupt requestto the processor. The interrupt request to the processor does not clear if a higher priority interrupt requestarrives. Even in this case, INTVEC does not update to the higher priority request until the lower priorityinterrupt request is acknowledged by reading the INTC_IACKR. The reading also pushes the PRI valuein the INTC current priority register (INTC_CPR) onto the LIFO and updates PRI in the INTC_CPR withthe priority of the interrupt request. The INTC_CPR masks any peripheral or software settable interruptrequest at the same or lower priority of the current value of the PRI field in INTC_CPR from generatingan interrupt request to the processor.The interrupt exception handler must write to the end-of-interrupt register (INTC_EOIR) to complete theoperation. Writing to the INTC_EOIR ends the servicing of the interrupt request. The INTC’s LIFO ispopped into the INTC_CPR's PRI field by writing to the INTC_EOIR, and the size of a write does notaffect the operation of the write. Those values and sizes written to this register neither update theINTC_EOIR contents nor affect whether the LIFO pops. For possible future compatibility, write four bytesof all 0s to the INTC_EOIR. The timing relationship between popping the LIFO and disabling recognitionof external input has no restriction. The writes can happen in either order.However, disabling recognition of the external input before popping the LIFO eases the calculation of themaximum stack depth at the cost of postponing the servicing of the next interrupt request.10.1.4.2 Hardware Vector ModeIn hardware vector mode, the interrupt exception handler address is specific to the peripheral or softwaresettable interrupt source rather than being common to all of them. No IVOR is used. The interruptexception handler address is calculated by hardware as shown in Figure 10-6. The upper half of theinterrupt vector prefix register (IVPR) is added to an offset which corresponds to the peripheral or softwareinterrupt source which caused the interrupt request. The offset matches the value in the Interrupt Vectorfield, INTC_IACKR[INTVEC]. Each interrupt exception handler address is aligned on a four-word(16-byte) boundary. IVOR4 is not used in this mode, and software does not need to read INTC_IACKR toget the interrupt vector number.3116150IVPR31282716150+ IVOR4312827161500x000x00OFFSETOFFSETPREFIX0x0000PREFIX= Interrupt exception0x0000handler address
