NXP Semiconductors MPC5566 Reference Manual Manual pdf 299 page image
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NXP Semiconductors MPC5566 Reference Manual

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Contents
  1. MPC5566 Reference Manual,
  2. MPC5566 Reference Manual Addendum, Rev
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Table Of Contents
  34. Table Of Contents
  35. Table Of Contents
  36. Table Of Contents
  37. Table Of Contents
  38. Table Of Contents
  39. Table Of Contents
  40. Table Of Contents
  41. Table Of Contents
  42. Table Of Contents
  43. Table Of Contents
  44. Table Of Contents
  45. Table Of Contents
  46. Table Of Contents
  47. MPC5566 Microcontroller Reference Manual, Rev
  48. Rev.
  49. Features
  50. MPC5500 Family Comparison
  51. Detailed Features
  52. System Bus Crossbar Switch (XBAR)
  53. Frequency Modulated Phase-Locking Loop (FMPLL)
  54. Cache
  55. Enhanced Management Input/Output System (eMIOS)
  56. Enhanced Serial Communications Interface (eSCI)
  57. Fast Ethernet Controller (FEC)
  58. MPC5500 Family Memory Map
  59. Multi-Master Operation Memory Map
  60. Block Diagram
  61. External Signal Descriptions
  62. Device Signals Summary
  63. Detailed Signal Description
  64. Reset and Configuration Signals
  65. RSTCFG_GPIO[210]
  66. External Address / Master Address Expansion / GPIO ADDR[30:31]_ADDR[6:7]_GPIO[26:27]
  67. DATA[22]_FEC_RXD[0]_GPIO[50]
  68. DATA[30]_FEC_RXD[2]_GPIO[58]
  69. TEA_FEC_RXD[3]_GPIO[71]
  70. MDO[0]
  71. JCOMP
  72. CNRXC_PCSD[4]_GPIO[88]
  73. SOUTA_PCSC[5]_GPIO[95]
  74. SCKB_PCSC[1]_GPIO[102]
  75. PCSB[4]_SCKC_GPIO[109]
  76. AN[5]_DAN2–
  77. AN[12]_MA[0]_SDS
  78. AN[16:39]
  79. ETPUA[0]_ETPUA[12]_GPIO[114]
  80. ETPUA[6]_ETPUA[18]_GPIO[120]
  81. ETPUA[13]_PCSB[3]_GPIO[127]
  82. ETPUA[21]_IRQ[9]_GPIO[135]
  83. TCRCLKB_IRQ[6]_GPIO[146]
  84. EMIOS[13]_SOUTD_GPIO[192]
  85. eMIOS Channel /eTPU B Output Channel / GPIO EMIOS[20:21]_ETPUB[4:5]_GPIO[199:200]
  86. Calibration Bus Signals
  87. CAL_TS
  88. VDDAn
  89. VDDEHn
  90. eTPU Pin Connections and Serialization
  91. ETPUA[16:31]
  92. ETPUB[0:31]
  93. eMIOS Pin Connections and Serialization
  94. Introduction
  95. Overview
  96. Instruction Unit Features
  97. MMU Features
  98. Core Registers and Programmer's Model
  99. Power Architecture Registers
  100. Supervisor-Level Only Registers
  101. Core-Specific Registers
  102. e200z6 Core Complex Features Not Supported in the Device
  103. Functional Description
  104. Translation Flow
  105. Effective to Real Address Translation
  106. MMU Assist Registers (MAS[0:4], MAS[6])
  107. MAS[1] Register
  108. MAS[2] Register
  109. MAS[3] Register
  110. MAS[6] Register
  111. L1 Cache
  112. Cache Organization
  113. Cache Line Replacement Algorithm
  114. L1 Cache Control and Status Register 0 (L1CSR0)
  115. L1 Cache Configuration Register 0 (L1CFG0)
  116. Interrupt Types
  117. Bus Interface Unit (BIU)
  118. Signal Processing Extension APU (SPE APU)
  119. External References
  120. External Signal Description
  121. Reset Configuration (RSTCFG)
  122. System Reset Control Register (SIU_SRCR)
  123. Reset Sources
  124. External Reset
  125. Loss-of-Clock Reset
  126. Checkstop Reset
  127. Software System Reset
  128. RSTCFG Pin
  129. PLLCFG[0:1] Pins
  130. Invalid RCHW
  131. Reset Configuration Timing
  132. Reset Flow
  133. Master Privilege Control Register (PBRIDGE_x_MPCR)
  134. ripheral Access Control Registers (PBRIDGE_x_OPACR)
  135. Read Cycles
  136. Detailed Signal Descriptions
  137. Reset Output (RSTOUT)
  138. I/O Weak Pullup Reset Configuration (WKPCFG)
  139. External Interrupts
  140. Edge-Detect Events
  141. Register Descriptions
  142. MCU ID Register (SIU_MIDR)
  143. Reset Status Register (SIU_RSR)
  144. External Interrupt Status Register (SIU_EISR)
  145. DMA Interrupt Request Enable Register (SIU_DIRER)
  146. DMA/Interrupt Request Select Register (SIU_DIRSR)
  147. Overrun Status Register (SIU_OSR)
  148. Overrun Request Enable Register (SIU_ORER)
  149. IRQ Rising-Edge Event Enable Register (SIU_IREER)
  150. IRQ Digital Filter Register (SIU_IDFR)
  151. Pad Configuration Registers (SIU_PCR)
  152. Pad Configuration Register 0 (SIU_PCR0)
  153. Pad Configuration Registers 1–3 (SIU_PCR1–SIU_PCR3)
  154. Pad Configuration Registers 4–7 (SIU_PCR4–SIU_PCR7)
  155. Pad Configuration Registers 23–25 (SIU_PCR23–SIU_PCR25)
  156. Pad Configuration Registers 26–27 (SIU_PCR26–SIU_PCR27)
  157. Pad Configuration Registers 44 (SIU_PCR44)
  158. Pad Configuration Registers 47 (SIU_PCR47)
  159. Pad Configuration Registers 49 (SIU_PCR49)
  160. Pad Configuration Registers 51 (SIU_PCR51)
  161. Pad Configuration Registers 52 (SIU_PCR52)
  162. Pad Configuration Registers 54 (SIU_PCR54)
  163. Pad Configuration Registers 55 (SIU_PCR55)
  164. Pad Configuration Registers 57 (SIU_PCR57)
  165. Pad Configuration Registers 58 (SIU_PCR58)
  166. Pad Configuration Registers 60–61 (SIU_PCR60–SIU_PCR61)
  167. Pad Configuration Register 62 (SIU_PCR62)
  168. Pad Configuration Registers 64–65 (SIU_PCR64–SIU_PCR65)
  169. Pad Configuration Register 68 (SIU_PCR68)
  170. Pad Configuration Register 70 (SIU_PCR70)
  171. Pad Configuration Register 72 (SIU_PCR72)
  172. Pad Configuration Register 73 (SIU_PCR73)
  173. Pad Configuration Register 82–75 (SIU_PCR82–SIU_PCR75)
  174. Pad Configuration Register 84 (SIU_PCR84)
  175. Pad Configuration Register 86 (SIU_PCR86)
  176. Pad Configuration Register 87 (SIU_PCR87)
  177. Pad Configuration Register 89 (SIU_PCR89)
  178. Pad Configuration Register 91 (SIU_PCR91)
  179. Pad Configuration Register 93 (SIU_PCR93)
  180. Pad Configuration Register 94 (SIU_PCR94)
  181. Pad Configuration Registers 96 (SIU_PCR96)
  182. Pad Configuration Registers 97 (SIU_PCR97)
  183. Pad Configuration Register 99 (SIU_PCR99)
  184. Pad Configuration Register 100 (SIU_PCR100)
  185. Pad Configuration Register 102 (SIU_PCR102)
  186. Pad Configuration Register 103 (SIU_PCR103)
  187. Pad Configuration Register 105 (SIU_PCR105)
  188. Pad Configuration Register 106 (SIU_PCR106)
  189. Pad Configuration Register 108 (SIU_PCR108)
  190. Pad Configuration Register 109 (SIU_PCR109)
  191. Pad Configuration Registers 111–112 (SIU_PCR111–SIU_PCR112)
  192. Pad Configuration Register 114–117 (SIU_PCR114–SIU_PCR117)
  193. Pad Configuration Register 118 (SIU_PCR118)
  194. Pad Configuration Register 120 (SIU_PCR120)
  195. Pad Configuration Register 121 (SIU_PCR121)
  196. Pad Configuration Registers 122–124 (SIU_PCR122–SIU_PCR124)
  197. Pad Configuration Register 126 (SIU_PCR126)
  198. Pad Configuration Registers 127–129 (SIU_PCR127–SIU_PCR129)
  199. Pad Configuration Register 134 (SIU_PCR134)
  200. Pad Configuration Register 135 (SIU_PCR135)
  201. Pad Configuration Register 137 (SIU_PCR137)
  202. Pad Configuration Registers 138–141 (SIU_PCR138–SIU_PCR141)
  203. Pad Configuration Register 145 (SIU_PCR145)
  204. Pad Configuration Registers 147–162 (SIU_PCR147–SIU_PCR162)
  205. Pad Configuration Registers 163 (SIU_PCR163–SIU_PCR166)
  206. Pad Configuration Registers 167–178 (SIU_PCR167–SIU_PCR178)
  207. Pad Configuration Register 189–190 (SIU_PCR189–SIU_PCR190)
  208. Pad Configuration Register 191 (SIU_PCR191)
  209. Pad Configuration Register 193 (SIU_PCR193)
  210. Pad Configuration Register 194 (SIU_PCR194)
  211. Pad Configuration Register 196 (SIU_PCR196)
  212. Pad Configuration Register 197 (SIU_PCR197)
  213. Pad Configuration Registers 199–200 (SIU_PCR199–SIU_PCR200)
  214. Pad Configuration Register 201 (SIU_PCR201)
  215. Pad Configuration Registers 203–204 (SIU_PCR203–SIU_PCR204)
  216. Pad Configuration Registers 206–207 (SIU_PCR206–SIU_PCR207)
  217. Pad Configuration Register 208 (SIU_PCR208)
  218. Pad Configuration Register 210 (SIU_PCR210)
  219. Pad Configuration Registers 211–212 (SIU_PCR211–SIU_PCR212)
  220. Pad Configuration Register 214 (SIU_PCR214)
  221. Pad Configuration Register 216 (SIU_PCR216)
  222. Pad Configuration Register 218 (SIU_PCR218)
  223. Pad Configuration Register 225–224 (SIU_PCR225–SIU_PCR224)
  224. Pad Configuration Register 229 (SIU_PCR229)
  225. Pad Configuration Registers 257–258 (SIU_PCR257–SIU_PCR258)
  226. Pad Configuration Register 261 (SIU_PCR261)
  227. Pad Configuration Register 262 (SIU_PCR262)
  228. Pad Configuration Register 265 (SIU_PCR265)
  229. Pad Configuration Register 267 (SIU_PCR267)
  230. Pad Configuration Registers 270–271 (SIU_PCR270–SIU_PCR271)
  231. Pad Configuration Register 275 (SIU_PCR275)
  232. Pad Configuration Register 278–293 (SIU_PCR278–SIU_PCR293)
  233. Pad Configuration Register 295–296 (SIU_PCR295–SIU_PCR296)
  234. Pad Configuration Register 299 (SIU_PCR299)
  235. GPIO Pin Data Input Registers 0–213 (SIU_GPDIn)
  236. eQADC Trigger Input Select Register (SIU_ETISR)
  237. External IRQ Input Select Register (SIU_EIISR)
  238. DSPI Input Select Register (SIU_DISR)
  239. Chip Configuration Register (SIU_CCR)
  240. External Clock Control Register (SIU_ECCR)
  241. Compare A Register High (SIU_CARH)
  242. Compare A Register Low (SIU_CARL)
  243. Compare B Register High (SIU_CBRH)
  244. Boot Configuration
  245. Reset Control
  246. GPIO Operation
  247. eQADC External Trigger Input Multiplexing
  248. SIU External Interrupt Input Multiplexing
  249. Modes of Operation
  250. Slave General-Purpose Control Registers (XBAR_SGPCRn)
  251. Master Ports
  252. Priority Assignment
  253. Parking
  254. Memory Map and Register Definition
  255. ECC Configuration Register (ECSM_ECR)
  256. ECC Error Generation Register (ECSM_EEGR)
  257. Flash ECC Address Register (ECSM_FEAR)
  258. Flash ECC Master Number Register (ECSM_FEMR)
  259. Flash ECC Data High Register (ECSM_FEDRH)
  260. Flash ECC Data Low Registers (ECSM_FEDRL)
  261. RAM ECC Address Register (ECSM_REAR)
  262. RAM ECC Master Number Register (ECSM_REMR)
  263. RAM ECC Data High Register (ECSM_REDRH)
  264. RAM ECC Data Low Registers (ECSM_REDRL)
  265. Initialization and Application Information
  266. eDMA Error Status Register (EDMA_ESR)
  267. eDMA Enable Request Registers (EDMA_ERQRH, EDMA_ERQRL)
  268. eDMA Enable Error Interrupt Registers (EDMA_EEIRH, EDMA_EEIRL)
  269. eDMA Set Enable Request Register (EDMA_SERQR)
  270. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
  271. eDMA Clear Interrupt Request Register (EDMA_CIRQR)
  272. eDMA Set START Bit Register (EDMA_SSBR)
  273. eDMA Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL)
  274. eDMA Error Registers (EDMA_ERH, EDMA_ERL)
  275. DMA Hardware Request Status (EDMA_HRSH, EDMA_HRSL)
  276. eDMA Channel n Priority Registers (EDMA_CPRn)
  277. Transfer Control Descriptor (TCD)
  278. eDMA Basic Data Flow
  279. eDMA Performance
  280. DMA Programming Errors
  281. DMA Request Assignments
  282. DMA Arbitration Mode Considerations
  283. Fixed-Group Arbitration, Round-Robin Channel Arbitration
  284. Multiple Requests
  285. Modulo Feature
  286. Active Channel TCD Reads
  287. Dynamic Programming
  288. Hardware Vector Mode
  289. INTC Current Priority Register (INTC_CPR)
  290. INTC End-of-Interrupt Register (INTC_EOIR)
  291. INTC Priority Select Registers (INTC_PSR0–329)
  292. Peripheral Interrupt Requests
  293. Unique Vector for Each Interrupt Request Source
  294. Vector Encoder Submodule
  295. Details on Handshaking with Processor
  296. Hardware Vector Mode Handshaking
  297. Software Vector Mode
  298. Order of Execution
  299. Priority Ceiling Protocol
  300. and Deadlines
  301. Scheduling an ISR on Another Processor
  302. Negating an Interrupt Request Outside of its ISR
  303. FMPLL and Clock Architecture
  304. FMPLL Bypass Mode
  305. FMPLL External Reference Mode
  306. FMPLL Crystal Reference Mode Without FM
  307. FMPLL Crystal Reference Mode With FM
  308. FMPLL Dual-Controller Mode (1:1)
  309. FMPLL Modes of Operation
  310. External Reference Mode
  311. Bypass Mode
  312. Synthesizer Status Register (FMPLL_SYNSR)
  313. Software Controlled Power Management/Clock Gating
  314. External Bus Clock (CLKOUT)
  315. Clock Operation
  316. FMPLL Loss-of-Lock Reset
  317. Programming System Clock Frequency Without Frequency Modulation
  318. Programming System Clock Frequency with Frequency Modulation
  319. FM Calibration Routine
  320. Module Disable Mode
  321. Debug Mode
  322. Burst Data in Progress (BDIP)
  323. Transfer Acknowledge (TA)
  324. Bus Busy (BB)
  325. Transfer Size 0 through 1 (TSIZ[0:1])
  326. Signal Function and Direction by Mode
  327. EBI Transfer Error Status Register (EBI_TESR)
  328. EBI Bus Monitor Control Register (EBI_BMCR)
  329. EBI Base Registers 0–3 (EBI_BRn and EBI Calibration Base Registers 0–3 (EBI_CAL_BRn)
  330. EBI Option Registers 0–3 (EBI_ORn) and EBI Calibration Option Registers
  331. Memory Controller with Support for Various Memory Types
  332. Burst Support (Wrapped Only)
  333. Port Size Configuration per Chip Select (16 or 32 Bits)
  334. Configurable Bus Speed Clock Modes
  335. Misaligned Access Support
  336. External Bus Operations
  337. External Clocking
  338. Single-Beat Transfer
  339. Single-Beat Write Flow
  340. Back-to-Back Accesses
  341. Burst Transfer
  342. Small Access Example #3: 32-byte Read to 32-bit Port with
  343. TBDIP Effect on Burst Transfer
  344. Small Accesses (Small Port Size and Short Burst Length)
  345. Small Access Example #1: 32-bit Write to 16-bit Port
  346. Size, Alignment, and Packaging on Transfers
  347. Arbitration
  348. External (or Central) Bus Arbiter
  349. Internal Bus Arbiter
  350. Termination Signals Protocol
  351. Bus Operation in External Master Mode
  352. Address Decoding for External Master Accesses
  353. Bus Transfers Initiated by an External Master
  354. Bus Transfers Initiated by the EBI in External Master Mode
  355. Back-to-Back Transfers in External Master Mode
  356. Non-Chip-Select Burst in 16-bit Data Bus Mode
  357. Calibration Bus Operation
  358. Running with Asynchronous Memories
  359. Timing and Connections for Asynchronous Memories
  360. Connecting an MCU to Multiple Memories
  361. Flash Memory Map
  362. MCR Simultaneous Register Writes
  363. Low/Mid Address Space Block Locking Register (FLASH_LMLR)
  364. High Address Space Block Locking Register (FLASH_HLR)
  365. Low/Mid Address Space Block Select Register (FLASH_LMSR)
  366. High Address Space Block Select Register (FLASH_HSR)
  367. Flash Bus Interface Unit Control Register (FLASH_BIUCR)
  368. Flash Bus Interface Unit Access Protection Register (FLASH_BIUAPR)
  369. FBIU Basic Interface Protocol
  370. FBIU Line Read Buffers and Prefetch Operation
  371. FBIU Per-Master Prefetch Triggering
  372. Read While Write (RWW)
  373. Software Locking
  374. Flash Erase Suspend/Resume
  375. Flash Shadow Block
  376. Flash Disable
  377. FLASH_BIUAPR Modification
  378. Flash Memory Array: Reset
  379. Register Memory Map
  380. Access Timing
  381. Reset Effects on SRAM Accesses
  382. Example Code
  383. Interface Options
  384. Top Level Module Memory Map
  385. Registers
  386. FEC Registers
  387. Ethernet Interrupt Mask Register (EIMR)
  388. Receive Descriptor Active Register (RDAR)
  389. Transmit Descriptor Active Register (TDAR)
  390. Ethernet Control Register (ECR)
  391. MII Management Frame Register (MMFR)
  392. MII Speed Control Register (MSCR)
  393. MIB Control Register (MIBC)
  394. Receive Control Register (RCR)
  395. Transmit Control Register (TCR)
  396. Physical Address Low Register (PALR)
  397. Physical Address Upper Register (PAUR)
  398. Descriptor Individual Upper Address Register (IAUR)
  399. Descriptor Individual Lower Address (IALR)
  400. Descriptor Group Upper Address (GAUR)
  401. FIFO Transmit FIFO Watermark Register (TFWR)
  402. FIFO Receive Bound Register (FRBR)
  403. Receive Descriptor Ring Start (ERDSR)
  404. Transmit Buffer Descriptor Ring Start (ETDSR)
  405. Initialization Sequence
  406. Application Initialization (Prior to Asserting ECR[ETHER_EN])
  407. Microcontroller Initialization
  408. FEC Frame Transmission
  409. FEC Frame Reception
  410. Ethernet Address Recognition
  411. Hash Algorithm
  412. Full Duplex Flow Control
  413. Inter-Packet Gap (IPG) Time
  414. Ethernet Error-Handling Procedure
  415. Reception Errors
  416. Driver/DMA Operation with Transmit BDs
  417. Ethernet Receive Buffer Descriptor (RxBD)
  418. Ethernet Transmit Buffer Descriptor (TxBD)
  419. Serial Boot Mode
  420. BAM Program Operation
  421. Internal Boot Mode
  422. External Boot Modes
  423. Single Bus Master or Multiple Bus Masters
  424. Read the Reset Configuration Halfword
  425. Serial Boot Mode FlexCAN and eSCI Configuration
  426. Download Process for FlexCAN Serial Boot Mode
  427. eSCI Serial Boot Mode Download Process
  428. Interrupts
  429. eMIOS Operating Modes
  430. Output Disable Input—eMIOS Output Disable Input Signals
  431. Register Description
  432. eMIOS Global Flag Register (EMIOS_GFR)
  433. eMIOS Output Update Disable Register (EMIOS_OUDR)
  434. eMIOS Channel A Data Register (EMIOS_CADRn)
  435. eMIOS Channel Counter Register (EMIOS_CCNTRn)
  436. eMIOS Channel Status Register (EMIOS_CSRn)
  437. eMIOS Alternate Address Register (EMIOS_ALTAn)
  438. Effect of Freeze on the STAC Client Submodule
  439. Unified Channel (UC)
  440. Programmable Input Filter (PIF)
  441. Clock Prescaler (CP)
  442. General Purpose Input/Output Mode (GPIO)
  443. Single-action Output Compare Mode (SAOC)
  444. Input Pulse-Width Measurement Mode (IPWM)
  445. Input Period Measurement Mode (IPM)
  446. Double-action Output Compare Mode (DAOC)
  447. Pulse/Edge Accumulation Mode (PEA)
  448. Pulse and Edge Counting Mode (PEC)
  449. Quadrature Decode Mode (QDEC)
  450. Windowed Programmable Time Accumulation Mode (WPTA)
  451. Modulus Counter Mode (MC)
  452. Output Pulse-Width Modulation Mode (OPWM)
  453. Modulus Counter Buffered Mode (MCB)
  454. Output Pulse-Width Modulation, Buffered Mode (OPWMB)
  455. Initialization/Application Information
  456. eTPU Operation Overview
  457. eTPU Engine
  458. eTPU Timer Channels
  459. Shared Data Memory (SDM)
  460. Task Scheduler
  461. Microengine
  462. User Configuration Mode
  463. Output and Input Channel Signals
  464. Time Base Clock Signal (TCRCLKA and TCRCLKB)
  465. eTPU Register Addresses
  466. System Configuration Registers
  467. eTPU Coherent Dual-Parameter Controller Register (ETPU_CDCR)
  468. eTPU MISC Compare Register (ETPU_MISCCMPR)
  469. eTPU Engine Configuration Register (ETPU_ECR)
  470. Time Base Registers
  471. eTPU Time Base Configuration Register (ETPU_TBCR)
  472. eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)
  473. eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)
  474. STAC Bus Configuration Register (ETPU_REDCR)
  475. Global Channel Registers
  476. eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)
  477. eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)
  478. eTPU Channel Interrupt Enable Register (ETPU_CIER)
  479. eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)
  480. eTPU Channel Pending Service Status Register (ETPU_CPSSR)
  481. eTPU Channel Service Status Register (ETPU_CSSR)
  482. Channel Registers Layout
  483. eTPU Channel n Configuration Register (ETPU_CnCR)
  484. eTPU Channel n Status Control Register (ETPU_CnSCR)
  485. eTPU Channel n Host Service Request Register (ETPU_CnHSRR)
  486. Stop Mode
  487. eQADC Register Descriptions
  488. eQADC Null Message Send Format Register (EQADC_NMSFR)
  489. eQADC External Trigger Digital Filter Register (EQADC_ETDFR)
  490. eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn)
  491. eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn)
  492. eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn)
  493. eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)
  494. eQADC CFIFO Transfer Counter Registers 0–5 (EQADC_CFTCRn)
  495. eQADC CFIFO Status Register (EQADC_CFSR)
  496. eQADC SSI Control Register (EQADC_SSICR)
  497. eQADC SSI Receive Data Register (EQADC_SSIRDR)
  498. eQADC CFIFO Registers (EQADC_CF[0–5]Rn)
  499. eQADC RFIFO Registers (EQADC_RF[0–5]Rn)
  500. On-Chip ADC Registers
  501. ADCn Control Registers (ADC0_CR and ADC1_CR)
  502. ADC Time Stamp Control Register (ADC_TSCR)
  503. ADC Time Base Counter Registers (ADC_TBCR)
  504. Data Flow in the eQADC
  505. Assumptions/Requirements Regarding the External Device
  506. Command Execution and Result Return
  507. Message Formats for On-Chip ADC Operation
  508. Message Formats for External Device Operation
  509. Command/Result Queues
  510. CFIFO Prioritization and Command Transfer
  511. External Trigger from eTPU or eMIOS Channels
  512. CFIFO Scan Trigger Modes
  513. Single-Scan Mode
  514. Continuous-Scan Mode
  515. CFIFO Scan Trigger Mode Start/Stop Summary
  516. CFIFO and Trigger Status
  517. Command Queue Completion Status
  518. Pause Status
  519. Trigger Overrun Status
  520. Result FIFOs
  521. Distributing Result Data into RFIFOs
  522. On-Chip ADC Configuration and Control
  523. Time Stamp Feature
  524. MAC Unit and Operand Data Format
  525. ADC Control Logic Overview and Command Execution
  526. Internal/External Multiplexing
  527. External Multiplexing
  528. eQADC eDMA/Interrupt Request
  529. eQADC Synchronous Serial Interface (SSI) Submodule
  530. eQADC SSI Data Transmission Protocol
  531. Abort Feature
  532. Analog Submodule
  533. RSD Overview
  534. RSD Adder
  535. Initialization of On-Chip ADCs and an External Device
  536. Configuring eQADC for Applications
  537. eQADC/eDMA Controller Interface
  538. Receive Queue/RFIFO Transfers
  539. Sending Immediate Command Setup Example
  540. Command Queue and Result Queue Usage
  541. ADC Result Calibration
  542. MAC Configuration Procedure
  543. Example Calculation of Calibration Constants
  544. eQADC versus QADC
  545. Peripheral Chip Select 4 / Master Trigger (PCSx[4]_MTRIG)
  546. DSPI Transfer Count Register (DSPIx_TCR)
  547. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
  548. DSPI Status Register (DSPIx_SR)
  549. DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
  550. DSPI POP RX FIFO Register (DSPIx_POPR)
  551. DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn)
  552. DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn)
  553. DSPI DSI Configuration Register (DSPIx_DSICR)
  554. DSPI DSI Serialization Data Register (DSPIx_SDR)
  555. DSPI DSI Alternate Serialization Data Register (DSPIx_ASDR)
  556. DSPI DSI Transmit Comparison Register (DSPIx_COMPR)
  557. DSPI DSI Deserialization Data Register (DSPIx_DDR)
  558. Master Mode
  559. Serial Peripheral Interface (SPI) Configuration
  560. FIFO Disable Operation
  561. Draining the TX FIFO
  562. Draining the RX FIFO
  563. DSI Slave Mode
  564. DSI Deserialization
  565. Change In Data Control
  566. DSPI B Connectivity
  567. DSPI C Connectivity
  568. DSPI D Connectivity
  569. Multiple Transfer Operation (MTO)
  570. Internal Muxing and SIU Support for Serial and Parallel Chaining
  571. Parallel Chaining
  572. Serial Chaining
  573. Combined Serial Interface (CSI) Configuration
  574. CSI Deserialization
  575. DSPI Baud Rate and Clock Delay Generation
  576. Peripheral Chip Select Strobe Enable (PCSS)
  577. Transfer Formats
  578. Classic SPI Transfer Format (CPHA = 0)
  579. Classic SPI Transfer Format (CPHA = 1)
  580. Modified Transfer Format Enabled (MTFE = 1) with Classic SPI Transfer Format Cleared (CPHA = 0) for SPI and DSI
  581. Modified Transfer Format Enabled (MTFE = 1) with Classic SPI Transfer Format Set (CPHA = 1) for SPI and DSI
  582. Continuous Selection Format
  583. Clock Polarity Switching between DSPI Transfers
  584. Interrupts and DMA Requests
  585. Transmit FIFO Underflow Interrupt Request (TFUF)
  586. Slave Interface Signal Gating
  587. Baud Rate Settings
  588. Delay Settings
  589. Calculation of FIFO Pointer Addresses
  590. Entry in the TX FIFO
  591. eSCI Control Register 2 (ESCIx_CR2)
  592. eSCI Data Register (ESCIx_DR)
  593. eSCI Status Register (ESCIx_SR)
  594. LIN Control Register (ESCIx_LCR)
  595. LIN Transmit Register (ESCIx_LTR)
  596. LIN Receive Register (ESCIx_LRR)
  597. LIN CRC Polynomial Register (ESCIx_LPR)
  598. Data Format
  599. Baud Rate Generation
  600. Transmitter
  601. Break Characters
  602. Fast Bit Error Detection in LIN Mode
  603. Receiver
  604. Character Reception
  605. Framing Errors
  606. Slow Data Tolerance
  607. Fast Data Tolerance
  608. Idle Input Line Wake-up (WAKE = 0)
  609. Loop Operation
  610. Disabling the eSCI
  611. Features of the LIN Hardware
  612. Generating an RX Frame
  613. LIN Error Handling
  614. LIN Setup
  615. Memory Map
  616. Message Buffer Structure
  617. Module Configuration Register (CANx_MCR)
  618. Control Register (CANx_CR)
  619. Free Running Timer (CANx_TIMER)
  620. RX Global Mask (CANx_RXGMASK)
  621. RX 14 Mask (CANx_RX14MASK)
  622. Error Counter Register (CANx_ECR)
  623. Error and Status Register (CANx_ESR)
  624. Interrupt Masks High Register (ICANx_IMRH)
  625. Interrupt Flags High Register (CANx_IFRH)
  626. Interrupt Flags Low Register (CANx_IFRL)
  627. Transmit Process
  628. Receive Process
  629. Reception Queue
  630. Notes on TX Message Buffer Deactivation
  631. CAN Protocol Related Features
  632. Time Stamp
  633. Arbitration and Matching Timing
  634. Module Disabled Mode
  635. Bus Interface
  636. FlexCAN2 Addressing and RAM Size
  637. POR Circuits
  638. V POR Circuit
  639. Compatible Power Transistors
  640. Pin Values after POR Negates
  641. IEEE 1149.1-2001 Defined Test Modes
  642. Bypass Register
  643. Enabling the TAP Controller
  644. BYPASS Instruction
  645. HIGHZ Instruction
  646. Reduced-Port Mode
  647. Test Data Input (TDI)
  648. NDI Functional Description
  649. Configuring the NDI for Nexus Messaging
  650. Programmable MCKO Frequency
  651. Nexus Port Controller (NPC)
  652. Port Configuration Register (PCR)
  653. NPC Functional Description
  654. Output Messages
  655. Rules of Messages
  656. Enabling the NPC TAP Controller
  657. Retrieving Device IDCODE
  658. Selecting a Nexus Client Register
  659. Nexus Auxiliary Port Sharing
  660. Nexus Reset Control
  661. e200z6 Class 3 Nexus Module (NZ6C3)
  662. Enabling Nexus3 Operation
  663. TCODEs Supported by NZ6C3
  664. NZ6C3 Memory Map and Register Definition
  665. Development Control Registers 1 and 2 (DC1, DC2)
  666. Development Status Register (DS)
  667. Read/Write Access Control and Status (RWCS)
  668. Read/Write Access Address (RWA)
  669. Watchpoint Trigger Register (WT)
  670. Data Trace Control Register (DTC)
  671. Data Trace Start Address Registers 1 and 2 (DTSAn)
  672. NZ6C3 Register Access via JTAG / OnCE
  673. Ownership Trace
  674. OTM Error Messages
  675. Branch Trace Messaging (BTM)
  676. BTM Using Branch History Messages
  677. BTM Message Formats
  678. Resource Full Messages
  679. Program Correlation Messages
  680. Program Trace Synchronization Messages
  681. BTM Operation
  682. Sequential Instruction Count (I-CNT)
  683. Data Trace
  684. Data Trace Messaging (DTM)
  685. DTM Overflow Error Messages
  686. DTM Operation
  687. Data Trace Timing Diagrams (Eight MDO Configuration)
  688. Watchpoint Support
  689. Watchpoint Error Message
  690. Watchpoint Timing Diagram (2 MDO and 1 MSEO Configuration)
  691. Single Write Access
  692. Block Write Access (Burst Mode)
  693. Block Read Access (Non-Burst Mode)
  694. Error Handling
  695. Examples
  696. IEEE‚ 1149.1 (JTAG) RD/WR Sequences
  697. JTAG Sequence for Read Access of Memory-Mapped Resources
  698. Nexus Crossbar eDMA Interface (NXDM)
  699. NXDM Nexus Register Map
  700. Development Control Registers (DC1 and DC2)
  701. Data Trace Start Address Registers 1 and 2 (DTSA1 and DTSA2)
  702. Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)
  703. Breakpoint / Watchpoint Control Register 2 (BWC2)
  704. Breakpoint/Watchpoint Address Registers 1 and 2 (BWA1 and BWA2)
  705. NXDM JTAG DID Register
  706. TCODEs Supported by NXDM
  707. Data Trace Synchronization Messages
  708. DTM Queueing
  709. Watchpoint Messaging
  710. A.1 Base Addresses of the Device Modules
  711. A.2 MPC5566 Register Map
  712. B.1 Overview
  713. B.2 Calibration Bus
  714. B.3 Device-Specific Information
  715. B.4.3 CLKOUT
  716. B.8 Application Information
  717. C.1 Changes Between Revisions 1 and 2
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MPC5566
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