NexusMPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 25-2525.7.2.8 Nexus Reset ControlThe JCOMP input that is used as the primary reset signal for the NPC is also used by the NPC to generatea single-bit reset signal for other Nexus modules. If JCOMP is negated, an internal reset signal is asserted,indicating that all Nexus modules should be held in reset. This internal reset signal is also asserted duringa power-on reset, or if nex_disable is asserted (SIU_CCR[DISNEX]), indicating the device is in censoredmode. This single bit reset signal functions much like the IEEE® 1149.1-2001 defined TRST signal andallows JCOMP reset information to be provided to the Nexus modules without each module having tosense the JCOMP signal directly or monitor the status of censored mode.25.8 NPC Initialization/Application Information25.8.1 Accessing NPC Tool-Mapped RegistersTo initialize the TAP for NPC register accesses, the following sequence is required:1. Enable the NPC TAP controller. This is achieved by asserting JCOMP and loading theACCESS_AUX_TAP_NPC instruction in the JTAGC.2. Load the TAP controller with the NEXUS-ENABLE instruction.To write control data to NPC tool-mapped registers, the following sequence is required:1. Write the 7-bit register index and set the write bit to select the register with a pass through theSELECT-DR-SCAN path in the TAP controller state machine.2. Write the register value with a second pass through the SELECT-DR-SCAN path. Note that theprior value of this register is shifted out during the write.To read status and control data from NPC tool-mapped registers, the following sequence is required:1. Write the 7-bit register index and clear the write bit to select register with a pass throughSELECT-DR-SCAN path in the TAP controller state machine.2. Read the register value with a second pass through the SELECT-DR-SCAN path. Data shifted inis ignored.Refer to the IEEE®-ISTO 5001-2003 standard for more detail.25.9 Nexus Dual eTPU Development Interface (NDEDI)The enhanced timing processor unit (eTPU) has its own Nexus class 3 interface, the Nexus dual eTPUdevelopment interface (NDEDI). The two eTPU engines and a coherent dual parameter controller (CDC)appear as three separate Nexus clients. Refer to the Enhanced Time Processor Unit Reference Manual formore information about the NDEDI module.
