MPC5566 Microcontroller Reference Manual, Rev. 222-24 Freescale Semiconductor22.3.3.11 Interrupt Flags Low Register (CANx_IFRL)CANx_IFRL defines the flags for 32 message buffer interrupts. It contains one interrupt flag bit per buffer.Each successful transmission or reception sets the corresponding IFRL bit. If the corresponding IMRL bitis set, an interrupt is generated. Write a 1 to the interrupt flag to clear its value to zero. Writing 0 has noeffect.22.4 Functional Description22.4.1 OverviewThe FlexCAN2 module is a CAN protocol engine with a very flexible message buffer configurationscheme. The module can have up to 64 message buffers, any of which can be assigned as either a TX bufferor an RX buffer. Each message buffer has an assigned interrupt flag to indicate successful completion oftransmission or reception.Table 22-15. CANx_IFRH Field DescriptionsField Description0–31BUFnIMessage buffer n interrupt. Each bit represents the respective FlexCAN2 message buffer (MB63–MB32)interrupt. Write 1 to clear.0 No such occurrence1 The corresponding buffer has successfully completed transmission or reception.Address: Base + 0x0030 Access: User R/W1c0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R BUF31IBUF30IBUF29IBUF28IBUF27IBUF26IBUF25BUF24IBUF23IBUF22IBUF21IBUF20IBUF19IBUF18IBUF17IBUF16IW w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R BUF15IBUF14IBUF13IBUF12IBUF11IBUF10IBUF09IBUF08IBUF07IBUF06IBUF05IBUF04IBUF03IBUF02IBUF01IBUF00IW w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 22-13. Interrupt Flags Low Register (CANx_IFRL)Table 22-16. CANx_IFRL Field DescriptionsField Description0–31BUFnIMessage buffer n interrupt. Each bit represents the respective FlexCAN2 message buffer (MB31 to MB0)interrupt. Write 1 to clear.0 No such occurrence1 The corresponding buffer has successfully completed transmission or reception.
